MC14554BCL 데이터 시트보기 (PDF) - Motorola => Freescale
부품명
상세내역
일치하는 목록
MC14554BCL Datasheet PDF : 6 Pages
| |||
ÎÎÎÎSÎÎÎÎWIÎÎÎÎTCHÎÎÎÎINGÎÎÎÎCHÎÎÎÎARÎÎÎÎAChCaÎÎÎÎTrEacRtÎÎÎÎeISriTsÎÎÎÎtIiCcSÎÎÎÎ* (CÎÎÎÎL=5ÎÎÎÎ0pFÎÎÎÎ,TAÎÎÎÎ=2ÎÎÎÎ5_CÎÎÎÎ)SymÎÎÎÎbolÎÎÎÎÎÎÎÎVÎÎÎÎDDÎÎÎÎÎÎÎÎÎÎÎÎMinÎÎÎÎÎÎÎÎTÎÎÎÎypÎÎÎÎ# ÎÎÎÎÎÎÎÎMaxÎÎÎÎÎÎÎÎUÎÎÎÎnitÎÎÎÎ
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
ns
tTHL
5.0
100
200
10
—
50
100
15
—
40
80
Propagation Delay Time
K0 to C0
tPLH, tPHL = (1.7 ns/pF) CL + 185 ns
tPLH, tPHL = (0.66 ns/pF) CL + 82 ns
tPLH, tPHL = (0.5 ns/pF) CL + 60 ns
M0 to S2
tPLH, tPHL = (1.7 ns/pF) CL + 595 ns
tPLH, tPHL = (0.66 ns/pF) CL + 247 ns
tPLH, tPHL = (0.5 ns/pF) CL + 185 ns
tPLH,
ns
tPHL
5.0
—
270
675
10
—
115
290
15
—
85
215
5.0
—
680
1700
10
—
280
750
15
—
210
570
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
20 ns
20 ns
ALL INPUTS
(50% DUTY CYCLE)
90%
50%
10%
1
2f
ANY OUTPUT
(50% DUTY CYCLE)
All outputs connected to respective
CL loads. f = system clock frequency
Figure 1. Dynamic Power Dissipation
Waveforms
20 ns
20 ns
90%
VDD
50%
INPUT
K0 OR M0
10%
tPLH
tPHL
VSS
90%
VOH
VDD
OUTPUT
10%
50%
VOL
VSS
C0 OR S2
tTLH
tTHL
VOH
For K0 to C0:
Inputs X0, X1, Y0, Y1, K1, and M2 low, and inputs
VOL
M0 and M1 high.
For M0 to S2:
Inputs X1, Y1, and K0 low, and inputs X0, Y0,
K1, M1, and M2 high.
Figure 2. Dynamic Signal Waveforms
LOGIC DIAGRAM
M1 Y1
M0 Y0
3
1
MY
X
MULTIPLIER
4
CELL
C0 C
K
S
2
15
MY
MULTIPLIER X
CELL
C
K
S
14
X0
12
K0
MULTIPLIER CELL
5
M2
M
S
Y
M
Y
MULTIPLIER X
MY
MULTIPLIER X
13
X1
X
K
L
C
CELL
CELL
10
C
KC
K
K1
S
S
6
7
9
11
C1(S3) S2
S1
S0
MOTOROLA CMOS LOGIC DATA
MC14554B
3
Share Link: 