MC100E256FN 데이터 시트보기 (PDF) - ON Semiconductor
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MC100E256FN Datasheet PDF : 8 Pages
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MC10E256, MC100E256
5VĄECL 3ĆBit 4:1 MuxĆLatch
The MC10E/100E256 contains three 4:1 multiplexers followed by
transparent latches with differential outputs. Separate Select controls
are provided for the leading 2:1 mux pairs (see logic symbol).
When the Latch Enable (LEN) is LOW, the latch is transparent, and
output data is controlled by the multiplexer select controls. A logic
HIGH on LEN latches the outputs. The Master Reset (MR) overrides
all other controls to set the Q outputs LOW.
The 100 Series contains temperature compensation.
• 950 ps Max. D to Output
• 850 ps Max. LEN to Output
• Split Select
• Differential Outputs
• PECL Mode Operating Range: VCC= 4.2 V to 5.7 V
with VEE= 0 V
• NECL Mode Operating Range: VCC= 0 V
with VEE= –4.2 V to –5.7 V
• Internal Input Pulldown Resistors
• ESD Protection: > 1 KV HBM, > 75 V MM
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL–94 code V–0 @ 1/8”,
Oxygen Index 28 to 34
• Transistor Count = 280 devices
http://onsemi.com
MARKING
DIAGRAMS
MC10E256FN
AWLYYWW
PLCC–28
FN SUFFIX
28 1
CASE 776
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
MC100E256FN
AWLYYWW
28 1
ORDERING INFORMATION
Device
Package
Shipping
MC10E256FN
PLCC–28 37 Units/Rail
MC10E256FNR2 PLCC–28 500 Units/Reel
MC100E256FN
PLCC–28 37 Units/Rail
MC100E256FNR2 PLCC–28 500 Units/Reel
© Semiconductor Components Industries, LLC, 2001
1
February, 2001 – Rev. 4
Publication Order Number:
MC10E256/D
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