MB88155 데이터 시트보기 (PDF) - Fujitsu

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MB88155

Spread Spectrum Clock Generator

Fujitsu 

MB88155

■ LOCK-UP TIME

VDD

3.0 V External clock

stabilization waiting time

XIN

XPD

VIH

SEL

VIH

ENS

CKOUT

tLK (Lock-up time)

If the XPD pin is fixed at the “H” level, the maximum time after the power is turned on until the set clock signal is

output from CKOUT pin is (the stabilization wait time of input clock to XIN pin) + (the lock-up time “tLK”). For the

input clock stabilization time, check the characteristics of the resonator or oscillator used.

VDD

XIN

XPD

SEL

ENS

CKOUT

3.0 V External clock

stabilization waiting time

VIH

VIH

tLK (Lock-up time)

If the XPD pin is used for power-down control, the set clock signal is output from the CKOUT pin at most the lock-

up time “tLK” after the XPD pin goes “H” level.

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