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MB86626

KeyWave™ AFE ADSL Analog Front End

Fujitsu 

January 2002 Version 1.2

FME/MS/ADSLAFE/FL_1/4282

MB86626 KeyWave™AFE ADSL Analog Front End

Transmit and Receive Channel

The receiver front end has constant resistance programmable attenuators on both receive inputs to

allow for variable line lengths, and to maintain sufficient dynamic range in the programmable gain low

noise summing amplifiers. Anti-aliasing filters are included which have programmable cut-off

frequency and gain control. SNR can be improved by matching the line impedance with the use of

the hybrid balance trim input which reduces echo signals prior to analog/digital echo cancellation

being applied. The ADC uses a proprietary error correcting successive approximation architecture

(patent applied for). In the Central Office the ADC conversion rates are halved compared to Remote

Terminal equipment to reduce power consumption. The attenuators, summing amplifier and filter give

a total gain from input to ADC of 0 to +38dB.

The transmit path features dual DACs and anti-imaging filters with programmable cut-off frequency

and gain. The dual DACs can be configured for oversampling parallel operation for Central Office

use, by internally summing the two Tx outputs. For Remote Terminal the DACs are used

independently for transmit and echo cancellation.

Data and Serial Control Interfaces

Data is transferred to and from the device via a 16-bit data bus. This bus can be configured as either

two byte-wide uni-directional data buses, with one byte for transmit and echo cancellation data and

one byte for receive data, or a single 16-bit bi-directional bus.

The device configuration registers are programmed via a 4-wire serial interface. These registers are

16-bit wide, and are individually accessed using an 8-bit address and control word. Data may be

written to or read from each of these registers.

Clock Multiplier

The device requires a clock source which may be an external reference, or a VCXO which can be

locked to the line symbol rate. The internal clock multiplier generates an internal clock which is then

divided down to provide all required internal and interface clocks. The clock multiplier is a delay line

based design and therefore provides no rejection of input clock jitter.

VCXO Control

The integral VCXO control provides an effective means of controlling an external VCXO clock source.

This digital output uses a first order Sigma-Delta DAC programmed from a 20-bit register. External

RC filtering would normally be provided.

Comparator Function

The KeyWave™AFE features a differential comparator which, for example, may be used to detect

whether the telephone on the subscriber line is ‘on or off hook’.

Copyright © 2002 Fujitsu Microelectronics Europe GmbH

Page 3 of 6

Disclaimer: The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before

ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.

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