MAX9880A 데이터 시트보기 (PDF) - Maxim Integrated

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MAX9880A

Low-Power, High-Performance Dual I2S Stereo Audio Codec

Maxim Integrated 

Low-Power, High-Performance

Dual I2S Stereo Audio Codec

ELECTRICAL CHARACTERISTICS (continued)

(VAVDD = VPVDD = VMICVDD = VDVDD = VDVDDS1 = +1.8V, RL = ∞, headphone load (RL) connected between _OUTP and _OUTN, dif-

ferential modes, CREF = 2.2µF, CMICBIAS = CPREG = CREG = 1µF, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB,

AVVOL = 0dB, AVLO = 0dB, fMCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)

PARAMETER

Bus Capacitance

Pulse Width of

Suppressed Spike

SYMBOL

CB

tSP

CONDITIONS

MIN

TYP MAX UNITS

400

pF

0

50

ns

SPI TIMING CHARACTERISTICS

Minimum SCLK Clock

Period

tCP

40

ns

Minimum SCLK Pulse-

Width Low

tCL

18

ns

Minimum SCLK Pulse-

Width High

Minimum CS Setup

Time

Minimum CS Hold Time

Minimum CS Pulse-

Width High

tCH

tCSS

tCSH

tCSW

18

ns

20

ns

20

ns

20

ns

Minimum DIN Setup Time tDS

Minimum DIN Hold Time

tDH

Minimum Output Data

Propagation Delay

tDO CL = 50pF

5

ns

5

ns

9

ns

Minimum Output Data

Enable Time

tDEN

5

ns

Minimum Output Data

Disable Time

tDZ

5

ns

Note 2: The MAX9880A is 100% production tested at TA = +25°C. Specifications over temperature limits are guaranteed by

design.

Note 3: Clocking all zeros into the DAC. Master mode. Differential headphone mode.

Note 4: DAC performance measured at headphone outputs.

Note 5: Dynamic range measured using the EIAJ method. -60dBFS 1kHz output signal, A-weighted, and normalized to 0dBFS.

f = 20Hz to 20kHz.

Note 6: Performance measured using microphone inputs, unless otherwise stated.

Note 7: Performance measured using line inputs.

Note 8: Performance measured using line inputs to line outputs.

Note 9: Performance measured using DAC. fMCLK = 12.288MHz, fLRCLK = 48kHz, unless otherwise stated.

Note 10: LRCLK can be any rate in the indicated range. Asynchronous or noninteger MCLK/LRCLK ratios can exhibit some full-

scale performance degradation compared to synchronous integer-related MCLK/LRCLK ratios.

Note 11: In master-mode operation, the accuracy of the MCLK input proportionally determines the accuracy of the sample clock

rate.

Note 12: CB is in pF.

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