MAX5580AEUP 데이터 시트보기 (PDF) - Maxim Integrated
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MAX5580AEUP Datasheet PDF : 34 Pages
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Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
TIMING CHARACTERISTICS—DSP Mode Disabled (1.8V Logic) (Figure 1)
(DVDD = 1.8V to 2.7V, AGND = DGND = 0, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SCLK Frequency
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS Fall to SCLK Rise Setup Time
SCLK Rise to CS Rise Hold Time
SCLK Rise to CS Fall Setup TIme
DIN to SCLK Rise Setup Time
DIN to SCLK Rise Hold Time
SCLK Rise to DOUTDC1 Valid
Propagation Delay
SYMBOL
fSCLK
tCH
tCL
tCSS
tCSH
tCS0
tDS
tDH
CONDITIONS
1.8V < DVDD < 2.7V
(Note 7)
(Note 7)
tDO1 CL = 20pF, UPIO_ = DOUTDC1 mode
MIN TYP
40
40
20
5
10
20
5
SCLK Fall to DOUT_ Valid
Propagation Delay
tDO2
CL = 20pF, UPIO_ = DOUTDC0 or DOUTRB
mode
CS Rise to SCLK Rise Hold Time
tCS1 MICROWIRE and SPI modes 0 and 3
20
CS Pulse-Width High
tCSW
90
UPIO_ TIMING CHARACTERISTICS
DOUT Tri-State Time when
Exiting DOUTDC0, DOUTDC1,
and UPIO Modes
tDOZ
CL = 20pF, from end of write cycle to UPIO_
in high impedance
DOUTRB Tri-State Time from CS
Rise
tDRBZ
CL = 20pF, from rising edge of CS to UPIO_
in high impedance
DOUTRB Tri-State Enable Time
from 8th SCLK Rise
LDAC Pulse-Width Low
LDAC Effective Delay
CLR, MID, SET Pulse-Width Low
GPO Output Settling Time
GPO Output High-Impedance
Time
tZEN
CL = 20pF, from 8th rising edge of SCLK to
UPIO_ driven out of tri-state
tLDL
Figure 5
40
tLDS Figure 6
200
tCMS Figure 5
40
tGP
Figure 6
tGPZ
MAX
10
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
60
ns
60
ns
ns
ns
200
ns
40
ns
40
ns
ns
ns
ns
200
ns
200
ns
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