MAX536ACPE(2011) 데이터 시트보기 (PDF) - Maxim Integrated

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MAX536ACPE
(Rev.:2011)

Calibrated, Quad, 12-Bit Voltage-Output DACs with Serial Interface

Maxim Integrated 

Calibrated, Quad, 12-Bit

Voltage-Output DACs with Serial Interface

ELECTRICAL CHARACTERISTICS—MAX537 (continued)

(VDD = +5V, VSS = -5V, REFAB/REFCD = 2.5V, AGND = DGND = 0V, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless

otherwise noted. Typical values are at TA = +25°C.)

PARAMETER

CS Fall to SDO Enable

CS Rise to DSO Disable (Note 10)

SCK Rise to CS Fall Delay

CS Rise to SCK Rise Hold Time

LDAC Pulse Width High

CS Pulse Width High

SYMBOL

tDV

tTR

tCSO

tCS1

tLDAC

tCSW

CONDITIONS

CLOAD = 50pF, MAX537_C/E

CLOAD = 50pF, MAX537_C/E

Continuous SCK, SCK edge ignored

SCK edge ignored, MAX537_C/E

MAX537_C/E

MAX537_C/E

MIN TYP MAX UNITS

75

140

ns

70

130

ns

35

ns

35

ns

50

ns

100

ns

Note 2: Guaranteed by design.

Note 3: Crosstalk is defined as the glitch energy at any DAC output in response to a full-scale step change on any other DAC.

Note 4: Digital inputs at 2.4V; with digital inputs at CMOS levels, IDD decreases slightly.

Note 5: All input signals are specified with tR = tF ≤ 5ns. Logic input swing is 0 to 5V.

Note 6: Serial data clocked out of SDO on SCK’s falling edge. (SDO is an open-drain output for the MAX536. The MAX537’s SDO

pin has an internal active pullup.)

Note 7: Serial data clocked out of SDO on SCK’s rising edge.

Note 10: When disabled, SDO is internally pulled high.

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