MAX520ACAP 데이터 시트보기 (PDF) - Maxim Integrated

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MAX520ACAP

Quad/Octal, 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs

Maxim Integrated 

Quad/Octal, 2-Wire Serial 8-Bit DACs

with Rail-to-Rail Outputs

ELECTRICAL CHARACTERISTICS (continued)

(VDD = 5V ±10%, VREF_ = 4V, RL = ∞ (MAX520), RL = 10kΩ (MAX521), CL = 0pF (MAX520), CL = 100pF (MAX521), TA = TMIN to TMAX,

unless otherwise noted. Typical values are at TA = +25°C)

PARAMETER

DYNAMIC PERFORMANCE

Voltage Output Slew Rate

SYMBOL

CONDITIONS

MAX521_C

Positive and negative MAX521_E

MAX521BM

MIN TYP MAX UNITS

1.0

0.7

V/µs

0.5

Output Settling Time

Digital Feedthrough

Digital-Analog Glitch Impulse

Signal to Noise + Distortion Ratio

Multiplying Bandwidth

Wideband Amplifier Noise

POWER REQUIREMENTS

Supply Voltage

Supply Current

MAX520_, to 1/2LSB, no load

MAX521_, to 1/2LSB, 10kΩ and

100pF load (Note 7)

2

µs

6

Code = 00 hex, all digital inputs from

0V to VDD

5

nV-s

Code 128 to 127

12

nV-s

SINAD

VREF_ = 4Vp-p at 1kHz, VDD = 5V,

code = FF hex

87

dB

VREF_ = 4Vp-p, 3dB bandwidth

MAX521_

1

MHz

60

µVRMS

VDD

4.5

5.5

V

Operating mode, out- MAX520_

put unloaded, all dig- MAX521_C

IDD

ital inputs 0V or VDD MAX521_E/BM

4

20

µA

10

20

mA

10

24

Power-down mode (PD = 1)

4

20

µA

Note 1: Input resistance is code dependent. The lowest input resistance occurs at code = 55 hex.

Note 2: Input capacitance is code dependent. The highest input capacitance occurs at code = FF hex.

Note 3: VREF_ = 4Vp-p, 10kHz. Channel-to-channel isolation is measured by setting the code of one DAC to FF hex and setting the

code of all other DACs to 00 hex.

Note 4: VREF_ = 4Vp-p, 10kHz, DAC code = 00 hex.

Note 5: Guaranteed by design.

Note 6: I2C-compatible mode.

Note 7: Output settling time is measured by taking the code from 00 hex to FF hex, and from FF hex to 00 hex.

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