MAX521ACAG 데이터 시트보기 (PDF) - Maxim Integrated
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MAX521ACAG Datasheet PDF : 20 Pages
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Quad/Octal, 2-Wire Serial 8-Bit DACs
with Rail-to-Rail Outputs
0 OR AD2
(a)
(RST)
0 1 0 1 AD1 AD0 0 0 0 0 0 1 0
0
SDA
XXX
ADDRESS BYTE
ACK
COMMAND BYTE
ACK
START
STOP
CONDITION
(b)
0 OR AD2
ALL INPUT LATCHES CONDITION
( ) SET TO 0
ALL OUTPUTS
( ) (RST)
SET TO 0
0 1 0 1 AD1 AD0 0 0 0 0 0 1 0
0
0
SDA
XXX XXXXXXXX
START
CONDITION
ADDRESS BYTE
NOTE: X = DON'T CARE
ACK
COMMAND BYTE
ACK
"DUMMY"
OUTPUT BYTE
( ) ALL INPUT LATCHES
SET TO 0
ACK ADDITIONAL
COMMAND BYTE/
OUTPUT BYTE PAIRS
STOP
CONDITION
( ) ALL DAC OUTPUTS SET TO 0 UNLESS
CHANGED BY ADDITIONAL COMMAND
BYTE/OUTPUT BYTE PAIRS
Figure 10. Resetting DAC Outputs
Setting the RST bit high clears all DAC input latches.
The DAC outputs remain unchanged until a STOP con-
dition is detected (Figure 10a). If a reset is issued, the
following output byte is ignored. Subsequent pairs of
command/output bytes overwrite the input latches
(Figure 10b).
All changes made during a transmission affect the
MAX520/MAX521’s outputs only when the transmission
ends and a STOP has been recognized. The R0, R1,
and R2 bits are reserved bits that must be set to zero.
I2C Compatibility
The MAX520/MAX521 are fully compatible with existing
I2C systems. SCL and SDA are high-impedance inputs;
SDA has an open drain which pulls the data line low
during the 9th clock pulse. Figure 11 shows a typical
I2C application.
Additional START Conditions
It is possible to interrupt a transmission to a MAX520/
MAX521 with a new START (repeated start) condition
(perhaps addressing another device), which leaves the
input latches with data that has not been transferred to
the output latches (Figure 12). Only the currently
addressed device will recognize a STOP condition and
transfer data to its output latches. If the device is left
with data in its input latches, the data can be trans-
ferred to the output latches the next time the device is
addressed, as long as it receives at least one com-
mand byte and a STOP condition.
µC
SDA SCL
E2 PROM
XICOR
X24C04
SCL
SDA
QUAD
DAC
MAX520
SCL
SDA
AD0
AD1
AD2
OCTAL
DAC
+5V
MAX521
SCL
SDA
AD0
AD1
Figure 11. Typical I2C Application Circuit
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