Low-Voltage, Dual DPDT/Quad SPDT
Analog Switches in QFN
Test Circuits/Timing Diagrams (continued)
MAX4699
MAX4701
MAX4702
VGEN
RGEN NC_
OR NO_
GND
V+
V+
COM_
IN
VIL TO VIH
Figure 4. Charge Injection
V+ 10nF
V OR V+
50Ω
IN_
V+
COM_
NC_
MAX4699
MAX4701
MAX4702 NO_
GND
VOUT
CL
VOUT
IN_
OFF
∆VOUT
OFF
ON
ON
OFF
OFF
IN_
Q = (∆VOUT)(CL)
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
NETWORK
ANALYZER
VIN
50Ω
50Ω
VOUT
MEAS
50Ω
REF
50Ω
OFF-ISOLATION = 20log VOUT
VIN
ON-LOSS
=
20log
VOUT
VIN
CROSSTALK = 20log
VOUT
VIN
MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT IC TERMINALS.
OFF-ISOLATION IS MEASURED BETWEEN COM_ AND "OFF" NO_ OR NC_ TERMINAL ON EACH SWITCH.
ON-LOSS IS MEASURED BETWEEN COM_ AND "ON" NO_ OR NC_TERMINAL ON EACH SWITCH.
CROSSTALK IS MEASURED FROM ONE CHANNEL TO ALL OTHER CHANNELS.
SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WORST VALUES ARE RECORDED.
Figure 5. On-Loss, Off-Isolation, and Crosstalk
10nF V+
CAPACITANCE
METER
f = 1MHz
V+
COM_
MAX4699
MAX4701
NC_ or
MAX4702
IN_
VIL
OR
VIH
NO_
GND
Chip Information
TRANSISTOR COUNT: 269
Substrate connected to GND
Figure 6. Channel Off/On-Capacitance
_______________________________________________________________________________________ 9