MAX3980 데이터 시트보기 (PDF) - Maxim Integrated
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MAX3980 Datasheet PDF : 9 Pages
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3.125Gbps XAUI Quad Equalizer
IN+
IN-
ESD
STRUCTURES
VCC
1.2kΩ
50Ω
50Ω
200μA
VCC
50Ω
50Ω
Q1
Q2
DATA
OUT+
OUT-
ESD
STRUCTURES
Figure 2. CML Input Buffer
Figure 3. CML Output Buffer
Signal Detect with Standby Mode
Signal activity is detected on channel 1 only. When the
peak-to-peak differential voltage at IN1± is less than
30mVp-p, the TTL output SDET goes low. When the
peak-to-peak differential voltage becomes greater than
100mVp-p, SDET is asserted high. SDET can be used
to automatically force the equalizer into standby mode
by connecting SDET directly to the EN input. When not
used, SDET should not be connected.
The signal-detect function continues to operate while
the part is in standby mode. While connected to the EN
pin, the signal detect can “wake up” the part and
resume normal operation.
Layout Considerations
Circuit-board layout and design can significantly affect
the MAX3980 performance. Use good high-frequency
design techniques, including minimizing ground induc-
tances and vias and using controlled-impedance trans-
mission lines for the high-frequency data signals.
Signals should be routed differentially to reduce EMI
susceptibility and crosstalk. Power-supply decoupling
capacitors should be placed as close as possible to
the VCC pins.
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