MT8982AC 데이터 시트보기 (PDF) - Mitel Networks
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MT8982AC Datasheet PDF : 14 Pages
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MT8982 ISO-CMOS
STi0 1
STi1 2
STo0 3
STo1 4
RxD/CSTi0 5
TxD/NC 6
SCLK/CSTi1 7
VSS 8
16 VDD
15 ODE
14 IC
13 MPS
12 F0o
11 F0i
10 C4i
9 CS
16 PIN CERDIP/PLASTIC/SOIC
STi0
STi1
NC
STo0
STo1
RxD/CSTi0
TxD/NC
NC
SCLK/CSTi1
VSS
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
20 PIN SSOP
Pin Description
Figure 2 - Pin Connections
VDD
ODE
IC
MPS
F0o
NC
F0i
NC
C4i
CS
Pin #
16 20
Name
Description
1-2 1-2 STi0- Serial TDM Input 0 and 1 (Inputs). 2048 kbit/s input data streams containing 32 8-bit
STi1 channels synchronized to F0i.
3-4 4-5 STo0- Serial TDM Output 0 and 1 (Outputs). 2048 kbit/s output data streams containing 32
STo1 8-bit channels synchronized to F0i.
5 6 RxD/ Received Data/Control Stream Input 0 (Input). When MPS is low, this pin receives serial
CSTi0 microport data clocked in by the rising edge SCLK. When MPS is high, this pin receives a
2048 kbit/s serial TDM stream containing 32 8-bit channels, which are written into the
Connect Memory locations corresponding to STo0.
67
TxD Transmit Data (Output). When MPS is low, serial microport data is clocked out on this pin
by the falling edge of SCLK. When MPS is high this output is disabled.
7 9 SCLK/ Serial Microport Clock/Control Stream Input 1 (Input). When MPS is low, this pin
CSTi1 receives a clock which is used to clock data to/from a microcontroller via a serial microport.
When MPS is high, this pin receives a 2048 kbit/s serial TDM stream containing 32 8-bit
channels, which are written into the Connect Memory locations corresponding to STo1.
8 10 VSS Power Input. Negative supply (ground).
9 11
CS Chip Select (Input). When MPS is low, a low on this pin enables the serial microport. A
high on this pin disables RxD and tristates TxD. When MPS is high, this pin must be low.
10 12
C4i Serial TDM Clock (Input). This clock input is used to clock the TDM data into and out of
the device and refreshes the internal dynamic RAM. The clock rate is 4.096 MHz and data
is clocked in on the rising edge of C4i three-quarters of the way through a bit period.
11 14
F0i Frame Pulse (Input). This input is the frame synchronization pulse for the 2048 kbit/s
serial TDM streams. It may be either active low stradling the frame boundary (ST-BUS) or
active high at the beginning of timeslot 5 (GCI).
12 16
F0o Frame Pulse (Output). This pin outputs a frame pulse in the opposite format to F0i (GCI
or ST-BUS) delayed or advanced by five channels.
13 17 MPS Microport Select (Input). When this pin is held low, the serial microport is in normal mode.
When this pin is high, the microport is in serial bus mode.
14 18
IC Internal Connection. Tie to VSS for normal operation.
15 19
ODE
Output Drive Enable (Input). When this pin is held high, the STo0 and STo1 output drivers
function normally. When this pin is low, STo0 and STo1 are tristated.
NB: When ODE is high, individual channels on STo0 and STo1 can be tristated under
software control.
16 20 VDD Power Input. Positive supply.
3,8, NC No Connection.
13,15
2-32
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