MAX199ACAI 데이터 시트보기 (PDF) - Maxim Integrated

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MAX199ACAI

Multi-Range (±4V, ±2V, +4V, +2V), +5V Supply, 12-Bit DAS with 8+4 Bus Interface

Maxim Integrated 

Multi-Range (±4V, ±2V, +4V, +2V),

+5V Supply, 12-Bit DAS with 8+4 Bus Interface

______________________________________________________________Pin Description

PIN NAME

1

CLK

2

CS

3

WR

4

RD

5

HBEN

6

7–10

11

12

13

14

15

16–23

24

SHDN

D7–D4

D3/D11

D2/D10

D1/D9

D0/D8

AGND

CH0–CH7

INT

25 REFADJ

26

REF

27

VDD

28

DGND

FUNCTION

Clock Input. In external clock mode, drive CLK with a TTL/CMOS compatible clock. In internal clock mode,

place a capacitor (CCLK) from this pin to ground to set the internal clock frequency; fCLK = 1.56MHz typical

with CCLK = 100pF.

Chip Select, active low.

When CS is low, in the internal acquisition mode, a rising edge on WR latches in configuration data and starts an

acquisition plus a conversion cycle. When CS is low, in the external acquisition mode, the first rising edge on

WR starts an acquisition and a second rising edge on WR ends acquisition and starts a conversion cycle.

When CS is low, a falling edge on RD will enable a read operation on the data bus.

Used to multiplex the 12-bit conversion result. When high, the 4 MSBs are multiplexed on the data bus;

when low, the 8 LSBs are available on the bus.

Shutdown. Puts the device into full power-down (FULLPD) mode when pulled low.

Three-State Digital I/O

Three-State Digital I/O. D3 output (HBEN = low), D11 output (HBEN = high).

Three-State Digital I/O. D2 output (HBEN = low), D10 output (HBEN = high).

Three-State Digital I/O. D1 output (HBEN = low), D9 output (HBEN = high).

Three-State Digital I/O. D0 output (HBEN = low), D8 output (HBEN = high). D0 = LSB.

Analog Ground

Analog Input Channels

INT goes low when conversion is complete and output data is ready.

Bandgap Voltage-Reference Output / External Adjust Pin. Bypass with a 0.01µF capacitor to AGND.

Connect to VDD when using an external reference at the REF pin.

Reference Buffer Output / ADC Reference Input. In internal reference mode, the reference buffer provides a

4.096V nominal output, externally adjustable at REFADJ. In external reference mode, disable the internal

buffer by pulling REFADJ to VDD.

+5V Supply. Bypass with 0.1µF capacitor to AGND.

Digital Ground

+5V

100k

24k

510k

0.01µF

MAX199

REFADJ

DOUT

3k

CLOAD

+5V

3k

DOUT

CLOAD

a) High-Z to VOH and VOL to VOH

b) High-Z to VOL and VOH to VOL

Figure 1. Reference-Adjust Circuit

Figure 2. Load Circuits for Enable Time

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