MAX199ACAI 데이터 시트보기 (PDF) - Maxim Integrated

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MAX199ACAI

Multi-Range (±4V, ±2V, +4V, +2V), +5V Supply, 12-Bit DAS with 8+4 Bus Interface

Maxim Integrated 

Multi-Range (±4V, ±2V, +4V, +2V),

+5V Supply, 12-Bit DAS with 8+4 Bus Interface

External Clock Mode

Select external clock mode by writing the control byte

with D7 = 0 and D6 = 0. Figure 8 shows CLK and WR

timing relationships in internal and external acquisition

modes, with an external clock. A 100kHz to 2.0MHz

external clock with 45% to 55% duty cycle is required

for proper operation. Operating at clock frequencies

lower than 100kHz will cause a voltage droop across

the hold capacitor, and subsequently degrade perfor-

mance.

ACQUISITION STARTS

ACQUISITION ENDS

CONVERSION STARTS

CLK

WR

tCWH

CLK

tCWS

ACQMOD = "0"

ACQUISITION STARTS

WR GOES HIGH WHEN CLK IS HIGH

ACQUISITION ENDS

CONVERSION STARTS

WR

ACQMOD = "0"

WR GOES HIGH WHEN CLK IS LOW

Figure 8a. External Clock and WR Timing (Internal Acquisition Mode)

ACQUISITION STARTS

ACQUISITION ENDS

CONVERSION STARTS

CLK

tDH

WR

ACQMOD = "1"

WR GOES HIGH WHEN CLK IS HIGH

tCWS

ACQMOD = "0"

ACQUISITION STARTS

ACQUISITION ENDS

CONVERSION STARTS

CLK

tDH

WR

ACQMOD = "1"

tCWH

WR GOES HIGH WHEN CLK IS LOW

ACQMOD = "0"

Figure 8b. External Clock and WR Timing (External Acquisition Mode)

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