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MAX1471ATJ/V Datasheet PDF : 26 Pages
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315MHz/434MHz Low-Power, 3V/5V
ASK/FSK Superheterodyne Receiver
AC ELECTRICAL CHARACTERISTICS (continued)
(Typical Application Circuit, VAVDD = VDVDD = VHVIN = +2.4V to +3.6V, fRF = 300MHz to 450MHz, TA = -40°C to +125°C, unless other-
wise noted. Typical values are at VAVDD = VDVDD = VHVIN = +3.0V, fRF = 434 MHz, TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
ANALOG BASEBAND
Maximum Data Filter Bandwidth
Maximum Data Slicer Bandwidth
Maximum Peak Detector
Bandwidth
SYMBOL
BWDF
BWDS
BWPD
Maximum Data Rate
CRYSTAL OSCILLATOR
Crystal Frequency
Frequency Pulling by VDD
fXTAL
Crystal Load Capacitance
DIGITAL INTERFACE TIMING (see Figure 8)
CONDITIONS
Manchester coded
Nonreturn to zero (NRZ)
MIN TYP MAX UNITS
50
kHz
100
kHz
50
kHz
33
kbps
66
9.04
13.728 MHz
3
ppm/V
3
pF
Minimum SCLK Setup to Falling
Edge of CS
tSC
30
ns
Minimum CS Falling Edge to
SCLK Rising-Edge Setup Time
Minimum CS Idle Time
Minimum CS Period
Maximum SCLK Falling Edge to
Data Valid Delay
tCSS
tCSI
tCS
tDO
30
ns
125
ns
2.125
µs
80
ns
Minimum Data Valid to SCLK
Rising-Edge Setup Time
tDS
30
ns
Minimum Data Valid to SCLK
Rising-Edge Hold Time
Minimum SCLK High Pulse Width
Minimum SCLK Low Pulse Width
Minimum CS Rising Edge to
SCLK Rising-Edge Hold Time
Maximum CS Falling Edge to
Output Enable Time
tDH
tCH
tCL
tCSH
tDV
30
ns
100
ns
100
ns
30
ns
25
ns
Maximum CS Rising Edge to
Output Disable Time
tTR
25
ns
Note 1: Production tested at TA = +85°C. Guaranteed by design and characterization over entire temperature range.
Note 2: Guaranteed by design and characterization. Not production tested.
Note 3: The oscillator register (0x3) is set to the nearest integer result of fXTAL / 100kHz (see the Oscillator Frequency Register section).
Note 4: Input impedance is measured at the LNAIN pin. Note that the impedance at 315MHz includes the 15nH inductive degeneration
from the LNA source to ground. The impedance at 434MHz includes a 10nH inductive degeneration connected from the LNA
source to ground. The equivalent input circuit is 50Ω in series with 2.2pF. The voltage conversion gain is measured with the
LNA input matching inductor, the degeneration inductor, and the LNA/mixer resonator in place, and does not include the IF fil-
ter insertion loss.
4 _______________________________________________________________________________________
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