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MAX147ACAP

+2.7V, Low-Power, 8-Channel, Serial 12-Bit ADCs

Maxim Integrated 

+2.7V, Low-Power, 8-Channel,

Serial 12-Bit ADCs

_______________Detailed Description

The MAX146/MAX147 analog-to-digital converters

(ADCs) use a successive-approximation conversion

technique and input track/hold (T/H) circuitry to convert

an analog signal to a 12-bit digital output. A flexible ser-

ial interface provides easy interface to microprocessors

(µPs). Figure 3 is a block diagram of the MAX146/

MAX147.

Pseudo-Differential Input

The sampling architecture of the ADC’s analog com-

parator is illustrated in the equivalent input circuit

(Figure 4). In single-ended mode, IN+ is internally

switched to CH0–CH7, and IN- is switched to COM. In

differential mode, IN+ and IN- are selected from the fol-

lowing pairs: CH0/CH1, CH2/CH3, CH4/CH5, and

CH6/CH7. Configure the channels with Tables 2 and 3.

In differential mode, IN- and IN+ are internally switched

to either of the analog inputs. This configuration is

pseudo-differential to the effect that only the signal at

IN+ is sampled. The return side (IN-) must remain sta-

ble within ±0.5LSB (±0.1LSB for best results) with

respect to AGND during a conversion. To accomplish

this, connect a 0.1µF capacitor from IN- (the selected

analog input) to AGND.

During the acquisition interval, the channel selected as

the positive input (IN+) charges capacitor CHOLD. The

acquisition interval spans three SCLK cycles and ends

on the falling SCLK edge after the last bit of the input

control word has been entered. At the end of the acqui-

sition interval, the T/H switch opens, retaining charge

on CHOLD as a sample of the signal at IN+.

The conversion interval begins with the input multiplex-

er switching CHOLD from the positive input (IN+) to the

negative input (IN-). In single-ended mode, IN- is sim-

ply COM. This unbalances node ZERO at the compara-

tor’s input. The capacitive DAC adjusts during the

remainder of the conversion cycle to restore node

ZERO to 0V within the limits of 12-bit resolution. This

action is equivalent to transferring a 16pF x [(VIN+) -

(VIN-)] charge from CHOLD to the binary-weighted

capacitive DAC, which in turn forms a digital represen-

tation of the analog input signal.

Track/Hold

The T/H enters its tracking mode on the falling clock

edge after the fifth bit of the 8-bit control word has been

shifted in. It enters its hold mode on the falling clock

edge after the eighth bit of the control word has been

shifted in. If the converter is set up for single-ended

inputs, IN- is connected to COM, and the converter

samples the “+” input. If the converter is set up for dif-

ferential inputs, IN- connects to the “-” input, and the

difference of |IN+ - IN-| is sampled. At the end of the

conversion, the positive input connects back to IN+,

and CHOLD charges to the input signal.

CS 18

SCLK 19

DIN 17

SHDN 10

CH0 1

CH1 2

CH2 3

CH3 4

CH4 5

CH5 6

CH6 7

CH7 8

COM 9

REFADJ 12

VREF 11

INPUT

SHIFT

REGISTER

CONTROL

LOGIC

INT

CLOCK

ANALOG

INPUT

MUX

OUTPUT

SHIFT

REGISTER

T/H

CLOCK

IN 12-BIT

SAR

ADC OUT

REF

+1.21V

REFERENCE

(MAX146)

A ≈ 2.06*

20k

+2.500V

MAX146

MAX147

15 DOUT

16 SSTRB

20 VDD

14 DGND

13 AGND

*A ≈ 2.00 (MAX147)

12-BIT CAPACITIVE DAC

VREF

CH0

INPUT

MUX

CHOLD

–+

COMPARATOR

ZERO

CH1

16pF

CH2

RIN

CH3

CSWITCH

9k

CH4

HOLD

CH5

TRACK

AT THE SAMPLING INSTANT,

CH6

CH7

T/H

SWITCH

THE MUX INPUT SWITCHES

FROM THE SELECTED IN+

CHANNEL TO THE SELECTED

COM

IN- CHANNEL.

SINGLE-ENDED MODE: IN+ = CH0–CH7, IN- = COM.

DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF

CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7.

Figure 3. Block Diagram

Figure 4. Equivalent Input Circuit

_______________________________________________________________________________________ 9

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