MAX1271ACAI 데이터 시트보기 (PDF) - Maxim Integrated

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MAX1271ACAI

Multirange, +5V, 8-Channel, Serial 12-Bit ADCs

Maxim Integrated 

Multirange, +5V, 8-Channel,

Serial 12-Bit ADCs

CS

SCLK

1

8

9 10

DIN

SSTRB

START SEL2 SEL1 SEL0 RNG BIP PD1 PD0

MSB

LSB

DOUT HIGH-Z

A/D STATE

16 INT CLK

HIGH-Z

ACQUISITION CONVERSION

D11 D10

MSB

2 EXT SCLK 12 INT CLK

+4 INT CLK

Figure 9. Internal Clock Mode—20 SCLK/Conversion Timing

19 20

D1 D0

LSB

FILLED WITH ZEROS

HIGH-Z

CS

SSTRB

SCLK

tCSH

tSSTRB

tCSS

tSCK

SCLK #8

NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.

Figure 10. Internal Clock Mode—SSTRB Detailed Timing

conversion in progress. Figure 10 shows the SSTRB

timing in internal clock mode.

Internal clock mode conversions can be completed

with 13 external clocks per conversion but require a

waiting period of 15µs for the conversion to be com-

pleted (Figure 11).

Most microcontrollers require that conversions occur in

multiples of 8 SCLK clock cycles. Sixteen clock cycles

per conversion (as shown in Figure 12) is typically the

most convenient way for a microcontroller to drive the

MAX1270/MAX1271.

Applications Information

Power-On Reset

The MAX1270/MAX1271 power up in normal operation

(all internal circuitry active) and internal clock mode,

waiting for a start bit. The contents of the output data

register are cleared at power-up.

Internal or External Reference

The MAX1270/MAX1271 operate with either an internal

or external reference. An external reference is connect-

ed to either REF or REFADJ (Figure 13). The REFADJ

internal buffer gain is trimmed to 1.638V to provide

4.096V at REF from a 2.5V reference.

14 ______________________________________________________________________________________

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