MAS9118 데이터 시트보기 (PDF) - Micro Analog systems

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MAS9118

Buzzer DAC Interface

Micro Analog systems 

GENERAL DESCRIPTION

Main features

The data path of MAS9118 consists of level shifters,

serial interface, interpolating digital to analog

converter (DAC) and balanced output driver (H-bridge).

MAS9118 produces PWM (pulse width modulated)

output signal according to the digital input data

sourced through DIN. Because of the PWM output

(class-D amplifier) there is no need for external

capacitors between MAS9118 output and load

element (no DC voltage at output).

The amplifier has excellent power efficiency due to

class-D operation. The driver distortion characteristic

is load insensitive.

The buzzer is driven in an H-bridge. The driver

balanced outputs double the voltage, which is

advantageous for portable devices with low voltage.

The device enters to a power-down mode after power-

on reset or when XRESET pin is low or when master

clock is stopped. Even though the device is internally

reset at start-up it is recommended to keep XRESET

low when switching powers on and rise XRESET

signal up later (a few ms after powers are switched

on). Output pins (OUTP, OUTN) are connected to

ground voltage (VSS) at power-down mode to prevent

some times harmful DC bias at output.

Interfaces

There are level shifters in the input (MCLK, CCLK,

DIN, XCS). Input level shifting provides the possibility

to use lower signal levels for device control and higher

signal level for buzzer driver, which enables higher

voltage to buzzer. The operating voltage of the driving

DA9118.000

11 May, 2000

circuit should be connected to VDDI, which is a

reference level for control signals.

The input signal is written into the internal register via

the asynchronous serial interface. Serial interface

consists of an input pin for data (DIN), chip select pin

(XCS) and control clock (CCLK).

CCLK has to be pulsed eight times while XCS is low

to shift the data in. The data is shifted into the serial

input register when 8 CCLK pulses has occurred after

XCS falling edge. When the eighth rising edge comes

the data is re-synchronized with MCLK and passed to

the DAC. XCS has to be set high before next data

can be read in (data read is started by XCS falling

edge). Input data read is cancelled if XCS is set high

before all 8 data bits has been read in, and old data

remains to device output.

The serial data word length is 8 bits and it is

2-complement with MSB first. The data (word) rate

(XCS falling edge -frequency), which is the device

output sampling frequency, should be in the range of

8 to 80 kHz for good audio quality.

The master clock (MCLK) is used for the on-chip

sigma-delta modulator, which truncates the 8-bit input

signal to 1-bit representation. The MCLK is used as a

DAC output sampling frequency. To minimize jitter,

MCLK should be integer multiple of the sampling

frequency (XCS frequency).

Since CCLK and MCLK are allowed to be

asynchronous, double buffering for input data is used

to guarantee correct operation in all conditions.

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