M95320-DL6 데이터 시트보기 (PDF) - STMicroelectronics
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M95320-DL6 Datasheet PDF : 39 Pages
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M95640, M95320
SUMMARY DESCRIPTION
These electrically erasable programmable memo-
ry (EEPROM) devices are accessed by a high
speed SPI-compatible bus. The memory array is
organized as 8192 x 8 bit (M95640), and 4096 x 8
bit (M95320).
The device is accessed by a simple serial interface
that is SPI-compatible. The bus signals are C, D
and Q, as shown in Table 1 and Figure 2.
The device is selected when Chip Select (S) is tak-
en Low. Communications with the device can be
interrupted using Hold (HOLD).
Figure 2. Logic Diagram
Figure 3. DIP and SO Connections
M95xxx
S1
Q2
8 VCC
7 HOLD
W3
6C
VSS 4
5D
AI01790D
VCC
D
C
S
W
HOLD
M95xxx
VSS
Q
AI01789C
Note: 1. See page 33 (onwards) for package dimensions, and how
to identify pin-1.
Figure 4. TSSOP14 Connections
M95xxx
S1
Q2
14 VCC
13 HOLD
NC 3
12 NC
NC 4
11 NC
NC 5
10 NC
W6
9C
VSS 7
8D
AI02346C
Note: 1. See page 33 (onwards) for package dimensions, and how
to identify pin-1.
2. NC = Not Connected
Table 1. Signal Names
C
Serial Clock
D
Serial Data Input
Q
Serial Data Output
S
Chip Select
W
Write Protect
HOLD
Hold
VCC
Supply Voltage
VSS
Ground
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