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M6759 Datasheet PDF : 8 Pages
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Acer Laboratories Inc.
M6759: 8 bit MTP Micro-controller
--Proprietary, Confidential, Preliminary--
Product Brief
Pin Description
Pin assignments shown below are listed based on 44-pin PLCC package. And if not additionally specified, further
pin number reference throughout this document is, by default, referred to 44-pin PLCC package. As for QFP
package, the pin number assignment should be shifted accordingly, as shown in Pinout Configuration.
Pin Name
VDD
GND
P0.7-P0.0
AD7-0
RST
XTAL1
XTAL2
/PSEN
ALE
P1.7-P1.0
T2EX (P1.1)
T2 (P1.0)
P2.7-P2.0
A15-A8
P3.7-P3.0
/RD (P3.7)
/WR (P3.6)
T1 (P3.5)
T0 (P3.4)
/INT1 (P3.3)
/INT0 (P3.2)
TXD (P3.1)
RXD (P3.0)
/EAVPP
NC
No. (PLCC) Type
44
IN
22
IN
36,37,38,39, I/O
40,41,42, 43
10
IN
21
IN
20
OUT
32
OUT
33
OUT
9,8,7,6,5,4,3, I/O
2
IN
IN
31,30,29,28, I/O
27,26,25, 24
OUT
19,18,17,16, I/O
15,14,13, 11
OUT
OUT
IN
IN
IN
IN
OUT
IN
35
IN
1,12,23,34 NC
Description
Power supply for internal operation, 5V input.
Ground.
Port 0 is 8 bits bi-directional I/O port with internal pull high.
Multiplexed address/data bus. During the time when ALE is high, the LSB of
a memory address is presented. When ALE falls, the port transitions to a
bi-directional data bus. This bus is used to read external ROM and read/write
external RAM memory or peripherals.
Reset signal of internal circuit, it must be kept 4 clocks to ensure being
recognized by internal circuit. This signal will not affect internal SRAM.
Crystal In, can be used as external clock input.
Crystal out, feedback of XTAL1.
Program Store Enable Output, commonly connected to external ROM
memory as a chip enable during fetching and MOVC operation. /PSEN goes
high during a reset condition.
Address Latch Enable, used to latch external LSB 8 bit address bus from
multiplexed address/data bus, commonly connect to the latch enable of 373
family. This signal will be forced high when the device is in a reset condition.
Port 1 is 8 bits bi-directional I/O port with internal pull high. All pins have an
alternate function shown as below.
External timer/counter 2 trigger.
External timer/counter 2.
Port 2 is 8 bits bi-directional I/O port with internal pull high. The alternate
function is MSB 8 bit address bus
This bus emits the high-order address byte during fetches from external
Program Memory or during accesses to external Data Memory that use 16-
bit addresses (MOVX @ DPTR).
During accesses to external Data Memory that use 8-bit addresses (MOVX
@ Ri), Port 2 emits the contents of the P2 Special Function Register.
Port 3 is an 8-bit bi-directional I/O port with internal pull high. The reset
condition of this port is with all bits at a logic 1.
Port 3 also have alternate function list below
External data memory read strobe.
External data memory write strobe.
External timer/counter 1.
External timer/counter 0.
External interrupt 1 (Negative Edge Detect).
External interrupt 0 (Negative Edge Detect).
Serial port output.
Serial port input.
The pin must be externally held low to enable the device to fetch code from
external program memory. If /EAVPP is held high, the device executes from
internal program memory. /EAVPP is internal latched on reset. This pin also
receives the 12V programming voltage (VPP) during FLASH programming.
These pins should not be connected for any purpose
Release date: 00/06/03, Document Number : 6759DS02
Page 3
Acer Labs: 11F, 45 Tung Hsing Road, Taipei 110, Taiwan, R.O.C. Tel: 886-2-8768-2800 Fax: 886-2-8768-3030
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