M5M4V64S20ATP-10L 데이터 시트보기 (PDF) - MITSUBISHI ELECTRIC

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M5M4V64S20ATP-10L

64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM

MITSUBISHI ELECTRIC  

SDRAM (Rev.1.3)

Mar98

MITSUBISHI LSIs

M5M4V64S20ATP-8A,-8L,-8, -10L, -10

64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM

BLOCK DIAGRAM DQ0-3

I/O Buffer

Memory Array Memory Array Memory Array Memory Array

Bank #0

Bank #1

Bank #2

Bank #3

Mode

Register

Control Circuitry

Address Buffer

Control Signal Buffer

A0-11 BA0,1

Clock Buffer

/CS /RAS /CAS /WE DQM

CLK CKE

Type Designation Code

This rule is applied to only Synchronous DRAM family.

M 5M 4 V 64 S 2 0 A TP - 8

Access Item

Package Type TP: TSOP(II)

Process Generation

Function 0: Random Column, 1: 2N-rule

Organization 2n 2: x4, 3: x8, 4: x16

Synchronous DRAM

Density 64:64M bits

Interface S: SSTL, V:LVTTL

Memory Style (DRAM)

Use, Recommended Operating Conditions, etc

Mitsubishi Main Designation

MITSUBISHI ELECTRIC

2

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