GLT6100L08LL-70TS 데이터 시트보기 (PDF) - G-Link Technology
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GLT6100L08LL-70TS Datasheet PDF : 10 Pages
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G-LINK
GLT6100L08
Ultra Low Power 128k x 8 CMOS SRAM
Nov 2000(Rev. 02)
Notes :
1. L-version includes this feature.
2. This Parameter is samples and not 100% tested.
3. For test conditions, see AC Test Condition.
4. This parameter is tested with CL = 5pF. Transition is measured ± 500mV from steady – state
voltage.
5. This parameter is guaranteed, but is not tested.
6. WE is HIGH for read cycle.
7. CE1 and OE are LOW and CE2 is HIGH for read cycle.
8. Address valid prior to or coincident with CE1 transition LOW or CE2 transition HIGH.
9. All read cycle timings are referenced from the last valid address to the first transtion address.
10. CE1 or WE must be HIGH or CE2 must be LOW during address transition.
11. All write cycle timings are referenced from the last valid address to the first transition address.
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