GLT6100L08LL-70ST 데이터 시트보기 (PDF) - G-Link Technology
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GLT6100L08LL-70ST Datasheet PDF : 10 Pages
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G-LINK
GLT6100L08
Ultra Low Power 128k x 8 CMOS SRAM
Nov 2000(Rev. 02)
Features :
Description :
∗ Low-power consumption.
-active: 30mA at 55ns.
-Stand by :
5 µA (CMOS input / output)
1 µA (CMOS input / output, SL)
∗ Single +2.7 to 3.3V Power Supply.
∗ Equal access and cycle time.
∗ 55/70/85/100 ns access time.
∗ Easy memory expansion with CE1 ,
CE2 and OE inputs.
∗ 2.0V data retention mode.
∗ TTL compatible, Tri-state input/output.
∗ Automatic power-down when
deselected.
The GLT6100L08 is a low power CMOS Static
RAM organized as 131,072 words by 8 bits. Easy
memory expansion is provided by an active LOW CE1
, an active HIGH CE2, an active LOW OE, and Tri-
state I/O’s. This device has an automatic power-
down mode feature when deselected.
Writing to the device is accomplished by taking
chip Enable 1 ( CE1 ) with Write Enable ( WE )
LOW, and Chip Enable 2 (CE2) HIGH. Reading from
the device is performed by taking Chip Enable 1 ( CE1
) with Output Enable ( OE ) LOW while Write Enable
( WE ) AND Chip Enable 2 (CE2) is HIGH. The I/O
pins are placed in a high-impedance state when the
device is deselected : the outputs are disabled during
a write cycle.
The GLT6100L08 comes with a 2V data retention
feature and Lower Standby Power. The GLT6100L08
is available in a 32-pin TSOPI / sTSOP / 48-fpBGA
packages.
Pin Configurations :
Function Block Diagram :
A11
1
A9
2
A8
3
A13
4
WE
5
CE2
6
A15
7
VCC
8
NC
9
A16
10
A14
11
A12
12
A7
13
A6
14
A5
15
A4
16
GLT6100L08
32
OE
31
A10
30
CE1
29
I/O8
28
I/O7
27
I/O6
26
I/O5
25
I/O4
24 GND
23
I/O3
22
I/O2
21
I/O1
20
A0
19
A1
18
A2
17
A3
INPUT BUFFER
A0
A1
A2
A3
1024
A4
x
A5
A6
1024
A7
A8
A9
COLUMN DECODER
A10 A11 A12 A13 A14 A15 A16
I/O8
I/O1
CONTROL
CIRCUIT
OE
WE
CE1
CE2
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
-1-
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
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