M38C88EA-XXXFP 데이터 시트보기 (PDF) - MITSUBISHI ELECTRIC
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M38C88EA-XXXFP Datasheet PDF : 51 Pages
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MITSUBISHI MICROCOMPUTERS
38C8 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMERS
The 38C8 group has five timers: timer X, timer Y, timer 1, timer 2, and
timer 3. Timer X and timer Y are 16-bit timers, and timer 1, timer 2,
and timer 3 are 8-bit timers.
All timers are down count timers. When the timer reaches “0016”, an
underflow occurs at the next count pulse and the corresponding timer
latch is reloaded into the timer and the count is continued. When a
timer underflows, the interrupt request bit corresponding to that timer
is set to “1”.
Read and write operation on 16-bit timer must be performed for both
high and low-order bytes. When reading a 16-bit timer, read the high-
order byte first. When writing to a 16-bit timer, write the low-order
byte first. The 16-bit timer cannot perform the correct operation when
reading during the write operation, or when writing during the read
operation.
f(XIN)/16
(f(XCIN)/16 in low-speed mode✽)
“00”,“11”
f(XIN)
Timer X count source
“1” selection bit
Data bus
f(XCIN)
“01”
“0”
Timer
mode
X operating
bits
CNTR0 active
edge switch bit
P42/CNTR0/BEEP+
“0”
“1”
Timer X operating
mode bits
“00”,“01”,“11”
“10”
Timer X stop control bit
Timer X write control bit
Timer X (low) latch (8) Timer X (high) latch (8)
Timer X (low) (8)
Timer X (high) (8)
Pulse width
measurement
mode
CNTR0 active
edge switch bit “0”
S
Q
Pulse output mode
P42 direction register
P42 latch
Buzzer output mode
T
Timer Y operating mode bits
“1” Q
“00”,“01”,“10”
Pulse width HL continuously
measurement mode
“11”
Rising edge detection
Falling edge detection
f(XIN)/16
(f(XCIN)/16 in low-speed mode✽)
Period measure-
ment mode
CNTR1 active
edge switch bit
“00”,“01”,“11”
Timer Y stop
control bit
Timer Y (low) latch (8)
Timer Y (low) high (8)
P43/CNTR1/BEEP-
“0”
Timer Y (low) (8)
Timer Y (high) (8)
“1”
“10” Timer Y operating
mode bits
Timer X interrupt
request
CNTR0 interrupt
request
CNTR1 interrupt
request
Timer Y interrupt
request
P43 direction register
P43 latch
BEEP- valid bit
f(XIN)/16
(f(XCIN)/16 in low-speed mode✽)
Timer 1 count source
selection bit “0”
f(XCIN)/32
“1”
Timer 1 latch (8)
Timer 1 (8)
Timer 2 count source
Timer 2 write control bit
selection bit
“0”
Timer 2 latch (8)
Timer 2 (8)
“1”
f(XIN)/16
(f(XCIN)/16 in low-speed mode✽)
Timer 1 interrupt
request
Timer 2 interrupt
request
f(XCIN)/32
“0”
Timer 3 latch (8)
Timer 3 (8)
“1”
Timer 3 count source
selection bit
✽ Internal clock φ = XCIN divided by 2 in low-speed mode
Fig. 16 Timer block diagram
20
Timer 3 interrupt
request
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