BS62LV2005STC-55 데이터 시트보기 (PDF) - Brilliance Semiconductor
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BS62LV2005STC-55 Datasheet PDF : 10 Pages
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BSI
WRITE CYCLE2 (1,6)
ADDRESS
CE1
CE2
WE
D OUT
D IN
BS62LV2005
t WC
(11)
t CW
(5)
t AS
(5)
t AW
(4,10)
t WHZ
(11)
t CW
t WP
(2)
t WR2
(3)
t DH
(7)
(8)
t DW
t DH
(8,9)
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low.
All signals must be active to initiate a write and any one signal can terminate a write by going
inactive. The data input setup and hold timing should be referenced to the second transition edge
of the signal that terminates the write.
3. TWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write
cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the
outputs must not be applied.
5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low
transitions or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input
signals of opposite phase to the outputs must not be applied to them.
10. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B. The
parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE1 going low or CE2 going high to the end of write.
R0201-BS62LV2005
7
Revision 2.4
April 2002
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