M37640E8FP 데이터 시트보기 (PDF) - Mitsumi

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M37640E8FP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Mitsumi 

Ver 1.4

MITSUBISHI MICROCOMPUTERS

7640 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

1.18.1 SIO Control Registers (SIOCON)

The Serial I/O Control Register 1 controls various SIO

functions such as transfer direction and transfer clock

divisor (see Figure 1.37). All of this register’s bits can

be read from and written to by software. At reset, this

register is cleared to 0016.

SIO Control Register 2 determines the transfer clock

phase and polarity, and also whether the SIO is to

function in SPI compatible mode (see Figure 1.38). All

of this register’s bits can be read from and written to

by software. At reset, this register is set to 1816.

MSB

7

OCHCont

SCSel

TDSel

R DY S e l

PSel

ISCSel2

ISCSel1

ISCSel0

LSB

0

Address: 002B16

Access: R/W

Reset: 4016

ISCSel0-2

PSel

RDYSel

TDSel

SCSel

OCHCont

Internal Synchronization Clock Select Bit (bits 2,1,0)

Bit 2

Bit 1

Bit 0

0

0

0 : Internal Clock Divided by 2

0

0

1 : Internal Clock Divided by 4

0

1

0 : Internal Clock Divided by 8

0

1

1 : Internal Clock Divided by 16

1

0

0 : Internal Clock Divided by 32

1

0

1 : Internal Clock Divided by 64

1

1

0 : Internal Clock Divided by 128

1

1

1: Internal Clock Divided by 256

SIO Port Selection Bit (bit 3)

0 : I/O Port

1 : TxD output, SCLK function

SRDY Output Select Bit (bit 4)

0 : I/O Port

1 : SRDY signal

Transfer Direction Select Bit (bit 5)

0 : LSB first

1 : MSB first

Synchronization Clock Select Bit (bit 6)

0 : External Clock

1 : Internal Clock

TxD Output Channel Bit (bit 7)

0 : CMOS output

1 : N-Channel open drain output

Fig. 1.37. SIO Control Register 1 (SIOCON1)

MSB

7

Reserved

Reserved

Reserved

CPha

CPol

RXDSel CLKSEL

SP1

LSB

0

Address: 002C16

Access: R/W

Reset: 1816

SPI

CLKSEL

RXDSel

CPol

CPHa

Bit 5-7

SPI Mode Selection Bit (bit 0)

0 : Normal SIO mode

1 : SPI compatibe mode

SIO Internal Clock Selection Bit (bit 1)

0: .

1: SCSGCLK

SRXD Input Selection Bit (bit 2)

0 : SRXD input disabled

1 : SRXD input enabled

Clock Polarity Selection Bit (bit 3)

0 : Clock is low between transfers

1 : Clock is high between transfers

Clock Phase Selection Bit (bit 4)

0 : Data is captured on the leading edge of serial clock, changes

on the following edge.

1 : Data changes on the leading edge of serial clock, captured on

the following edge.

Reserved (Read/Write “0”)

Fig. 1.38. SIO Control Register 2 (SIOCON2)

38

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