EDE5116GBSA-4A-E 데이터 시트보기 (PDF) - Elpida Memory, Inc

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EDE5116GBSA-4A-E

512M bits DDR-II SDRAM

Elpida Memory, Inc 

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA

Pin Function

CK, /CK (input pins)

CK and /CK are differential clock inputs. All address and control input signals are sampled on the crossing of the

positive edge of CK and negative edge of /CK. Output (read) data is referenced to the crossings of CK and /CK

(both directions of crossing).

/CS (input pin)

All commands are masked when /CS is registered High. /CS provides for external bank selection on systems with

multiple banks. /CS is considered part of the command code.

/RAS, /CAS, /WE (input pins)

/RAS, /CAS and /WE (along with /CS) define the command being entered.

A0 to A13 (input pins)

Provided the row address for Active commands and the column address and Auto Precharge bit for Read/Write

commands to select one location out of the memory array in the respective bank.

[Address Pins Table]

Address (A0 to A13)

Part number

Row address

EDE5104GB

AX0 to AX13

EDE5108GB

AX0 to AX13

EDE5116GB

AX0 to AX12

Notes: 1. A13 pin is NC for ×16 organization.

Column address

AY0 to AY9, AY11

AY0 to AY9

AY0 to AY9

Notes

1

A10 (AP) (input pin)

A10 is sampled during a precharge command to determine whether the precharge applies to one bank (A10 = Low)

or all banks (A10 = High). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address

inputs also provide the op-code during mode register set commands.

BA0, BA1 (input pins)

BA0 and BA1 define to which bank an active, read, write or precharge command is being applied. BA0 also

determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle.

[Bank Select Signal Table]

BA0

BA1

Bank 0

L

L

Bank 1

H

L

Bank 2

L

H

Bank 3

H

H

Remark: H: VIH. L: VIL.

CKE (input pin)

CKE High activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers.

Taking CKE Low provides precharge power-down and Self Refresh operation (all banks idle), or active power-down

(row active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is

asynchronous for self refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers,

excluding CK, /CK and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during self

refresh.

Preliminary Data Sheet E0249E30 (Ver. 3.0)

11

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