EDD5104ABTA-7A 데이터 시트보기 (PDF) - Elpida Memory, Inc

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EDD5104ABTA-7A

512M bits DDR SDRAM

Elpida Memory, Inc 

Block Diagram

CK

/CK

CKE

A0 to A12, BA0, BA1

/CS

/RAS

/CAS

/WE

EDD5104ABTA, EDD5108ABTA

Mode

register

Row

address

buffer

and

refresh

counter

Bank 3

Bank 2

Bank 1

Memory cell array

Bank 0

Column

address

buffer

and

burst

counter

CK, /CK

DLL

Sense amp.

Column decoder

Data control circuit

Latch circuit

Input & Output buffer

DQ

DQS

DM

Preliminary Data Sheet E0237E30 (Ver. 3.0)

10

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