WRITE CYCLE 2 (E Controlled, See Notes 1 and 2)
MCM32257B–15 MCM32257B–20 MCM32257B–25
Parameter
Symbol Min
Max
Min
Max
Min
Max Unit Notes
Write Cycle Time
tAVAV
15
—
20
—
25
—
ns
3
Address Setup Time
Address Valid to End of Write
tAVEL
0
—
0
—
0
—
ns
tAVEH
12
—
15
—
17
—
ns
Enable to End of Write
Enable to End of Write
Write Pulse Width
tELEH
10
—
12
—
15
—
ns
4,5
tELWH
10
—
12
—
15
—
ns
tWLEH
10
—
12
—
15
—
ns
Data Valid to End of Write
tDVEH
7
—
8
—
10
—
ns
Data Hold Time
tEHDX
0
—
0
—
0
—
ns
Write Recovery Time
tEHAX
0
—
0
—
0
—
ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. E1 – E4 are represented by E in these timing specifications, any combination of Exs may be asserted. G is a don’t care when W is low.
3. All write cycle timing is referenced from the last valid address to the first transitioning address.
4. If E goes low coincident with or after W goes low, the output will remain in a high impedance condition.
5. If E goes high coincident with or before W goes high, the output will remain in a high impedance condition.
A (ADDRESS)
Ex (BYTE ENABLE)
W (WRITE ENABLE)
D (DATA IN)
Q (DATA OUT)
WRITE CYCLE 2
tAVAV
tAVEH
tAVEL
tWLEH
HIGH–Z
tELEH
tELWH
tDVEH
DATA VALID
tEHAX
tEHDX
ORDERING INFORMATION
(Order by Full Part Number)
MCM 32257B X XX
Motorola Memory Prefix
Part Number
Speed (15 = 15 ns, 20 = 20 ns, 25 = 25 ns)
Package (Z = ZIP Module)
Full Part Numbers — MCM32257BZ15 MCM32257BZ20 MCM32257BZ25
MOTOROLA FAST SRAM
MCM32257B
6–7