M28C16 데이터 시트보기 (PDF) - STMicroelectronics

부품명

상세내역

일치하는 목록

M28C16

16K (2K x 8) PARALLEL EEPROM with SOFTWARE DATA PROTECTION

STMicroelectronics 

M28C16

Figure 3. Block Diagram

VPP GEN

RESET

E

G

W

CONTROL LOGIC

A6-A10

(Page Address)

ADDRESS

LATCH

A0-A5

ADDRESS

LATCH

64K ARRAY

Y DECODE

SENSE AND DATA LATCH

Page Write

Page write allows up to 64 bytes to be consecu-

tively latched into the memory prior to initiating a

programming cycle. All bytes must be located in a

single page address, that is A6-A10 must be the

same for all bytes. The page write can be initiated

during any byte write operation.

Following the first byte write instruction the host

may send another address and data with a mini-

mum data transfer rate of 1/tWHWH (see Figure 13).

If a transition of E or W is not detected within tWHWH,

the internal programming cycle will start.

Chip Erase

The contents of the entire memory may be erased

to FFh by use of the Chip Erase command by

setting Chip Enable (E) Low and Output Enable

(G) to VCC +7V. The chip is cleared when a 10ms

low pulse is applied to the Write Enable pin.

Figure 4. Status Bit Assignment

DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

DP TB PLTS Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z

DP = Data Polling

TB = Toggle Bit

PLTS = Page Load Timer Status

4/18

I/O BUFFERS

DQ0-DQ7

PAGE LOAD

TIMER STATUS

TOGGLE BIT

DATA POLLING

AI01520

Microcontroller Control Interface

The M28C16 provides two write operation status

bits and one status pin that can be used to minimize

the system write cycle. These signals are available

on the I/O port bits DQ7 or DQ6 of the memory

during programming cycle only.

Data Polling bit (DQ7). During the internal write

cycle, any attempt to read the last byte written will

produce on DQ7 the complementary value of the

previously latched bit. Once the write cycle is fin-

ished the true logic value appears on DQ7 in the

read cycle.

Toggle bit (DQ6). The M28C16 offers another way

for determining when the internal write cycle is

completed. During the internal Erase/Write cycle,

DQ6 will toggle from ”0” to ”1” and ”1” to ”0” (the

first read value is ”0”) on subsequent attempts to

read the memory. When the internal cycle is com-

pleted the toggling will stop and the device will be

accessible for a new Read or Write operation.

Page Load Timer Status bit (DQ5). In the Page

Write mode data may be latched by E or W. Up to

64 bytes may be input. The Data output (DQ5)

indicates the status of the internal Page Load

Timer. DQ5 may be read by asserting Output En-

able Low (tPLTS). DQ5 Low indicates the timer is

running, High indicates time-out after which the

write cycle will start and no new data may be input.

Share Link: