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LTC4307C

Low Offset Hot Swappable 2-Wire Bus Buffer with Stuck Bus Recovery

Linear Technology 

LTC4307

OPERATION

moment of connection, therefore minimizing the amount

of disturbance caused by the I/O card.

Once the LTC4307 comes out of UVLO, it monitors both

the backplane and card sides for either a stop bit or bus idle

condition to indicate the completion of data transactions.

When both sides are idle or one side has a stop bit condi-

tion while the other is idle, the input-to-output connection

circuitry is activated, joining the SDA and SCL busses on

the I/O card with those on the backplane. In addition, the

precharge circuitry is deactivated and will not be reactivated

unless the VCC voltage falls below the UVLO threshold.

Connection Circuitry

Once the connection circuitry is activated, the functionality

of the SDAIN and SDAOUT pins is identical. A low forced

on either pin at any time results in both pin voltages be-

ing low. The LTC4307 is tolerant of I2C bus DC logic low

voltages up to the 0.3VCC VIL I2C specification.

When the LTC4307 senses a rising edge on the bus, it

deactivates its pull-down devices for bus voltages as low

as 0.48V and activates its accelerators. This methodology

maximizes the effectiveness of the rise time accelerator

circuitry and maintains compatibility with the other devices

in the LTC4300 bus buffer family. Care must be taken to

ensure that devices participating in clock stretching or

arbitration force logic low voltages below 0.48V at the

LTC4307 inputs.

SDAIN and SDAOUT enter a logic high state only when

all devices on both SDAIN and SDAOUT release high.

The same is true for SCLIN and SCLOUT. This important

feature ensures that clock stretching, clock synchroniza-

tion, arbitration and the acknowledge protocol always

work, regardless of how the devices in the system are

tied to the LTC4307.

Another key feature of the connection circuitry is that it

provides bidirectional buffering, keeping the backplane

and card capacitances isolated. Because of this isolation,

the waveforms on the backplane busses look slightly

different than the corresponding card bus waveforms as

described here.

Input to Output Offset Voltage

When a logic low voltage, VLOW1, is driven on any of the

LTC4307’s data or clock pins, the LTC4307 regulates the

voltage on the opposite data or clock pins to a slightly

higher voltage, typically 60mV above VLOW1. This offset is

practically independent of pull-up current (see the Typical

Performance curves).

Propagation Delays

During a rising edge, the rise time on each side is de-

termined by the bus pull-up resistor and the equivalent

capacitance on the line. If the pull-up resistors are the

same, a difference in rise time occurs which is directly

proportional to the difference in capacitance between

the two sides. This effect is displayed in Figure 2 for

VCC = 5.5V and a 10k pull-up resistor on each side (50pF

on one side and 150pF on the other). Since the output

side has less capacitance than the input, it rises faster

and the effective propagation delay is negative.

There is a finite propagation delay through the connec-

tion circuitry for falling waveforms. Figure 3 shows the

falling edge waveforms for the same pull-up resistors and

equivalent capacitance conditions as used in Figure 2.

An external N-channel MOSFET device pulls down the

voltage on the side with 150pF capacitance; the LTC4307

pulls down the voltage on the opposite side with a delay

of 80ns. This delay is always positive and is a function

of supply voltage, temperature and the pull-up resistors

and equivalent bus capacitances on both sides of the bus.

The Typical Performance Characteristics section shows

propagation delay as a function of temperature and voltage

for 10k pull-up resistors and 50pF equivalent capacitance

on both sides of the part. Also, the tPHL vs COUT curve for

VCC = 5.5V shows that increasing the capacitance from

50pF to 150pF results in a tPHL increase from 81ns to 91ns.

Larger output capacitances translate to longer delays (up

to 125ns). Users must quantify the difference in propaga-

tion times for a rising edge versus a falling edge in their

systems and adjust setup and hold times accordingly.

4307f

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