LTC4306I 데이터 시트보기 (PDF) - Linear Technology
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LTC4306I Datasheet PDF : 20 Pages
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LTC4306
ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full specified temperature
range, otherwise specifications are at TA = 25°C. VCC = 3.3V unless otherwise noted.
SYMBOL
VALERT1-4(IN)
VALERT1-4(HY)
I2C Interface
VADR(H)
VADR(L)
IADR(IN, L)
PARAMETER
ALERT1-ALERT4 Pin Input Falling
Threshold Voltages
ALERT1-ALERT4 Pin Input Threshold
Hysteresis Voltages
ADR0-2 Input High Voltage
ADR0-2 Input Low Voltage
ADR0-2 Logic Low Input Current
CONDITIONS
ADR0-2 = 0V, VCC = 5.5V
MIN TYP MAX UNITS
● 0.8
1.0
1.2
V
80
mV
●
0.75 • VCC 0.9 • VCC
V
● 0.1 • VCC 0.25 • VCC
V
● –30 –60 –80
µA
IADR(FLOAT)
IADR(IN, H)
VSDAIN,SCLIN(TH)
ADRO-2 Allowed Input Current
ADR0-2 Logic High Input Current
SDAIN, SCLIN Input Falling Threshold
Voltages
VCC = 2.7V, 5.5V (Note 5)
ADR0-2 = VCC = 5.5V
VCC = 5.5V
VSDAIN,SCLIN(HY) SDAIN, SCLIN Hysteresis
ISDAIN,SCLIN(OH) SDAIN, SCLIN Input Current
CIN
SDA, SCL Input Capacitance
VSDAIN(OL)
SDAIN Output Low Voltage
I2C Interface Timing
SCL, SDA = VCC
(Note 2)
ISDA = 4mA, VCC = 2.7V
fSCL
tBUF
tHD,STA
tSU,STA
tSU,STO
tHD,DATI
tHD,DATO
tSU,DAT
tf
Maximum SCL Clock Frequency
(Note 2)
Bus Free Time Between Stop/Start Condition (Note 2)
Hold Time After (Repeated) Start Condition (Note 2)
Repeated Start Condition Set-up Time
(Note 2)
Stop Condition Set-up Time
(Note 2)
Data Hold Time Input
(Note 2)
Data Hold Time Output
(Note 2)
Data Set-up Time
(Note 2)
SCL, SDA Fall Times
(Note 2)
tSP
Pulse Width of Spikes Suppressed by the (Note 2)
Input Filter
●
±5
±13
µA
● 30
60
80
µA
● 1.4
1.6
1.8
V
30
mV
●
0
±5
µA
6
pF
●
0.2
0.4
V
400
kHz
0.75 1.3
µs
45
100
ns
–30
0
ns
–30
0
ns
–25
0
ns
300 600 900
ns
50
100
ns
20 + 0.1 •
CBUS
300
ns
50
150
250
ns
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Guaranteed by design and not subject to test.
Note 3: The boosted pull-up currents are regulated to prevent excessively
fast edges for light loads. See the Typical Performance Characteristics for
rise time as a function of VCC and parasitic bus capacitance CBUS and for
IBOOST as a function of VCC and temperature.
Note 4: When a logic low voltage, VLOW, is forced on one side of the
Upstream-Downstream Buffers, the voltage on the other side is regulated
to a voltage VLOW2 = VLOW + VOS, where VOS is a positive offset voltage.
VOS,UP-BUF is the offset voltage when the LTC4306 is driving the upstream
pin (e.g., SDAIN) and VOS,DOWN-BUF is the offset voltage when the
LTC4306 is driving the downstream pin (e.g., SDA1). See the Typical
Performance Characteristics for VOS,UP-BUF and VOS,DOWN-BUF as a
function of VCC and bus pull-up current.
Note 5: When floating, the ADR0-ADR2 pins can tolerate pin leakage
currents up to IADR(FLOAT) and still convert the address correctly.
4306f
4
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