LTC2619I 데이터 시트보기 (PDF) - Linear Technology

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LTC2619I

Quad 16-/14-/12-Bit Rail-to-Rail DACs with I2C Interface

Linear Technology 

LTC2609/LTC2619/LTC2629

PIN FUNCTIONS

GND (Pin 1): Analog Ground.

REFLO (Pin 2): Reference Low. The voltage at this pin

sets the zero-scale (ZS) voltage of all DACs. This pin can

be raised up to 1V above ground at VCC = 5V or 100mV

above ground at VCC = 3V.

REFA to REFD (Pins 3, 6, 12, 15): Reference Voltage

Inputs for each DAC. REFx sets the full-scale voltage of

the DACs. REFLO ≤ REFx ≤ VCC.

VOUTA to VOUTD (Pins 4, 5, 13, 14): DAC Analog Voltage

Outputs. The output range is from REFLO to REFx.

CA2 (Pin 7): Chip Address Bit 2. Tie this pin to VCC, GND

or leave it floating to select an I2C slave address for the

part (Table 1).

SCL (Pin 8): Serial Clock Input Pin. Data is shifted into

the SDA pin at the rising edges of the clock. This high

impedance pin requires a pull-up resistor or current

source to VCC.

SDA (Pin 9): Serial Data Bidirectional Pin. Data is shifted

into the SDA pin and acknowledged by the SDA pin. This

pin is high impedance pin while data is shifted in and is an

open-drain N-channel output during acknowledgment. SDA

requires a pull-up resistor or current source to VCC.

CA1 (Pin 10): Chip Address Bit 1. Tie this pin to VCC, GND

or leave it floating to select an I2C slave address for the

part (Table 1).

CA0 (Pin 11): Chip Address Bit 0. Tie this pin to VCC, GND

or leave it floating to select an I2C slave address for the

part (Table 1).

VCC (Pin 16): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V.

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