LTC1874 데이터 시트보기 (PDF) - Linear Technology
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LTC1874 Datasheet PDF : 12 Pages
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LTC1874
APPLICATIO S I FOR ATIO
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1874. These items are illustrated graphically for a
single controller in the layout diagram in Figure 6. Check
the following in your layout:
1. Is the Schottky diode closely connected between power
ground (PGND) and the drain of the external MOSFET?
2. Does the (+) plate of CIN connect to the sense resistor
as closely as possible? This capacitor provides AC
current to the MOSFET.
3. Is the input decoupling capacitor (0.1µF) connected
closely between VIN and signal ground (GND)?
4. Connect the end of RSENSE as close to VIN as possible.
The VIN pin is the SENSE + of the current comparator.
5. Is the trace from SENSE– to the SENSE resistor kept
short? Does the trace connect close to RSENSE?
6. Keep the switching node PGATE away from sensitive
small signal nodes.
7. Does the VFB pin connect directly to the feedback
resistors? The resistive divider R1 and R2 must be
connected between the (+) plate of COUT and signal
ground.
8. PVIN must connect to VIN and PGND must connect to
GND. Isolate high current power paths from signal
power and signal ground where possible in the layout.
An unbroken ground plane is recommended.
VIN
+
CIN
VOUT
+
R2
L1 SW
COUT
D1
R1
RSENSE
1/2 LTC1874
1
16
M1
VIN
PVIN
2 SENSE–
15
PGATE
0.1µF
3
14
GND
PGND
4
VFB
13
ITH/RUN
RITH
CITH
BOLD LINES INDICATE HIGH CURRENT PATHS
1874 F06
Figure 6. LTC1874 Layout Diagram (See PC Board Layout Checklist)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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