LT5524 데이터 시트보기 (PDF) - Linear Technology
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LT5524 Datasheet PDF : 16 Pages
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LT5524
APPLICATIO S I FOR ATIO
Application (Demo) Boards
The LT5524 demo boards are provided in the versions
shown in Figure 10 (with output transformer) and Fig-
ure 11 (without output transformer). All I/O signal ports
are matched to 50Ω. Moreover, 40k resistors (not shown)
connect all five control pins (EN, PGA0, PGA1, PGA2,
PGA3) to VCC, such that the LT5524 is shipped in maxi-
mum gain state.
The gain setting can be changed by connecting the control
pins to ground. Test points (TP1, TP2, TP3) are provided
to monitor the input and output DC bias voltage. Jumper
J1 can be removed when differential input is desired, but
in that case, T1 should be changed to a 1:1 center-tap
transformer to preserve 50Ω input matching. The demo
board is shipped with optional output back-matching
resistor RMATCH = 255Ω. This results in a net output load,
ROUT = 100Ω, presented to the LT5524.
The Output Transformer Application Board (Figure 10) is
one example of an output impedance transformation
(T2 transformer). For the Typical Performance Character-
istics curves, all linearity tests are performed on this
board. By removing RMATCH, the performance with ROUT
= 200Ω can be evaluated (provided the lack of impedance
back-matching is suitably remedied).
The transformer board can provide a differential output
when Jumper J2 is removed.
The Wideband Differential Output Application Board (Fig-
ure 11) is an example of direct coupling (no transformer)
to the load, and has wider output bandwidth. This board
gives direct access to the LT5524’s output pins, and was
used for stability tests. Higher VOSUP (6.5V) is required to
compensate for the DC voltage drop on R1 and R2. Use
TP2, TP3 to monitor the actual LT5524 output bias volt-
age. By replacing R1 and R2 with inductors, this board can
operate with a 5V supply. However, this may limit the
minimum signal frequency. For example, an 820nH choke
inductor will limit the lowest signal frequency to 40MHz.
VCC
C2
EN
0.1µF
1
20
EN
NC
NC
2
19
IF
IN
T1
3 VCC1
GND
VCC2 18
GND
1:2
4
LT5524
17
GND
GND
5 IN+
6 IN–
OUT– 16
OUT+ 15
ROUT
50Ω
7
14
J1
0Ω TC2-1T
C1
0.47µF
GND
8
GND
9
PGA0
GND
13
GND
12
PGA3
10
11
PGA1
PGA2
R1 R2
50Ω 50Ω
C4
0.1µF
VOSUP
C3
4.7µF
IF
OUT
C5
47nF
RLOAD
100Ω
C6
J2
47nF
0PEN
DIFFERENTIAL OUTPUT
RESISTIVE DEMO BOARD
PGA0 PGA1
PGA2 PGA3
5524 F11
Figure 11. Wideband Differential Output Application Board (Simplified Schematic)
5524f
14
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