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MAX122ACAG

500ksps, 12-Bit ADCs with Track/Hold and Reference

Maxim Integrated 

MAX120/MAX122

500ksps, 12-Bit ADCs with Track/Hold

and Reference

Figure 10. ROM Mode (Mode 4)

Figure 11. Continuous-Conversion Mode (Mode 5)

Mode 4: ROM Mode

(MODE = OPEN, CONVST = GND)

In ROM mode, the MAX120/MAX122 behave like a fast­

access memory location avoid placing the µP into a wait

state. Pulling RD and CS low places the T/H in hold mode,

starts a conversion, and reads data from the previous

conversion. Data from the first read in a sequence is often

disregarded when this interface mode is used. A second

read operation accesses the first conversion’s result and

also starts a new conversion. The time between succes-

sive read operations must be longer than the sum of the

T/H acquisition time and the MAX120/MAX122 conver-

sion time. See Figure 10 for ROM-mode timing.

Mode 5: Continuous-Conversion Mode

(CONVST = RD = CS = MODE = GND)

For systems that do not use or require full-bus interfacing,

the MAX120/MAX122 can operate in continuous-conver-

sion mode, directly linked to memory through DMA ports

or a FIFO buffer. In this mode, conversions are performed

Figure 12. Conversion-Control Logic

continuously at the rate of one conversion for every 14

clock cycles, which includes 2 clock cycles for the T/H

acquisition time. To satisfy the 350ns minimum acquisi-

tion time requirement within 2 clock cycles, the MAX120’s

maximum clock frequency is 6MHz when operating in

mode 5.

The data outputs are always enabled and “new” disap-

pears on the output bus at the end of a conversion as

indicated by the INT/BUSY output rising edge. The MODE

input should be hard-wired to GND. Pulling CS, RD,

or CONVST high stops conversions. See Figure 11 for

continuous-conversion mode timing.

Applications Information

Using FIFO Buffers

Using FIFO memory to buffer blocks of data from the

MAX120 reduces µP interrupt overhead time by enabling

the µP to process data while the MAX120, unassisted,

writes conversion results to the FIFO. To retrieve a block

of data, the µP reads from the FIFO via a read-interrupt

cycle. Read and write operations for the FIFO are com-

pletely asynchronous. Figure 13 shows the MAX120

operating in continuous-conversion mode (mode 5),writ-

ing data directly into the two IDT7200 256 x 9 FIFO buf-

fers at the rate of 428ksps. The µP is interrupted to read

the accumulated data by the FIFO’s half-full (HF) flag

approximately three times per millisecond. For operation

at 500ksps, use an 8MHz clock, and pulse CONVST at

500kHz. The full flag (FF) indicates that the FIFO is full.

If this flag is ignored, data may be lost. If necessary, con-

versions can be inhibited by pulling CS, RD, or CONVST

high. The FIFO’s read cycle times are as fast as 15ns,

satisfying most system speed requirements. The RESET

input resets all data in the FIFO to zero.

For synchronous operation, the CONVST pin may be

used to initiate conversions, as described in the Operating

Modes section (Mode 2: Stand-Alone Operation).

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