MAX122ACAG 데이터 시트보기 (PDF) - Maxim Integrated

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MAX122ACAG

500ksps, 12-Bit ADCs with Track/Hold and Reference

Maxim Integrated 

MAX120/MAX122

500ksps, 12-Bit ADCs with Track/Hold

and Reference

Figure 3. MAX120/MAX122 in the Simplest Operational Mode

(Continuous Conversion)

Internal Reference

The MAX120/MAX122 -5.00V buried-zener reference

biases the internal DAC. The reference output is available

at the VREF pin and must be bypassed to the AGND pin

with a 0.1µF ceramic capacitor in parallel with a 22µF or

greater electrolytic capacitor. The electrolytic capacitor’s

equivalent series resistance (ESR) must be 100mΩ or

less to properly compensate the reference output buffer.

Sanyo’s organic semiconductor works well.

Sanyo Video Components (USA)

Phone: (619) 661-6835

FAX: (619) 661-1055

Sanyo Electric Company, LTD. (Japan)

Phone: 0720-70-1005

FAX: 0720-70-1174

Sanyo Fisher Vertriebs GmbH (Germany)

Phone: 06102-27041, ext. 44 FAX: 06102-27045

Proper bypassing minimizes reference noise and main-

tains a low impedance at high frequencies. The internal

reference output buffer can sink up to a 5mA external load.

An external reference voltage can be used to overdrive

the MAX120/MAX122’s internal reference if it ranges from

-5.05V to -5.10V and is capable of sinking a minimum

of 5mA. The external VREF bypass capacitors are still

required.

Figure 4. Equivalent Input Circuit

Digital Interlace

External Clock

The MAX120/MAX122 require a TTL-compatible clock

for proper operation. The MAX120 accepts clocks in

the 0.1MHz to 8MHz frequency range when operating

in modes 1–4 (see the Operating Modes section). The

maximum clock frequency is limited to 6MHz when oper-

ating in mode 5. The MAX122 requires a 0.1MHz to 5MHz

clock for operation in all five modes. The minimum clock

frequency for both the MAX120 and MAX122 is limited to

0.1MHz, due to the T/H’s droop rate.

Clock and Control Synchronization

The clock and convert start inputs (CONVST or RD and

CS, see the Operating Modes section) are not synchro-

nized, the conversion time can vary from 13 to 14 clock

cycles. The successive approximation register (SAR)

always changes state on the CLKIN input’s rising edge.

To ensure a fixed conversion time, see Figure 5 and the

following guidelines.

For a conversion time of 13 clock cycles, the convert start

input(s) should go low at least 50ns before CLKIN’s next

rising edge. For a conversion time of 14 clock cycles,

the convert start input(s) should go low within 10ns of

CLKIN’s next rising edge. If the convert start input(s) go

low from 10ns to 50ns before CLKIN’s next rising edge,

the number of clock cycles required is undefined and can

be either 13 or 14. For best analog performance, synchro-

nize the convert start inputs with the clock input.

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