LP61L1024 데이터 시트보기 (PDF) - AMIC Technology
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LP61L1024 Datasheet PDF : 14 Pages
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LP61L1024
128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM
Features
Single +3.3V power supply
Access times: 12/15 ns (max.)
Current: Operating: 170mA (max.)
Standby: 10mA (max.)
Full static operation, no clock or refreshing required
All inputs and outputs are directly TTL compatible
Common I/O using three-state output
Output enable and two chip enable inputs for easy
application
Data retention voltage: 2.0V (min.)
Available in 32-pin SOJ 300 mil, 32-pin TSOP and 32-pin
TSSOP and 36-pin CSP packages
General Description
The LP61L1024 is a low operating current 1,048,576-bit static
random access memory organized as 131,072 words by 8 bits
and operates on a single 3.3V power supply.
Inputs and three-state outputs are TTL compatible and allow
for direct interfacing with common system bus structures.
Two chip enable inputs are provided for POWER-DOWN and
device enable and an output enable input is included for easy
interfacing.
Data retention is guaranteed at a power supply voltage as low
as 2.0V.
Product Family
Product
Family
Operating
Temperature
VCC
Range
Speed
Power Dissipation
Data Retention Standby Operating
(ICCDR, Typ.) (ISB1, Typ.) (ICC1, Typ.)
LP61L1024
0°C ~ 70°C 3V ~ 3.6V 12/15 ns
0.4mA
0.5mA
130mA
1. Typical values are measured at VCC = 3.0V, TA = 25°C and not 100% tested.
2. Data retention current VCC = 2.0V.
Package
Type
32L SOJ
32L TSOP
32L TSSOP
36B µBGA
(August, 2004, Version 2.2)
1
AMIC Technology, Corp.
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