LIS331DL 데이터 시트보기 (PDF) - STMicroelectronics
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LIS331DL
STMicroelectronics
LIS331DL Datasheet PDF : 42 Pages
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Mechanical and electrical specifications
LIS331DL
2.3
Communication interface characteristics
2.3.1
SPI - serial peripheral interface
Subject to general operating conditions for Vdd and top.
Table 5. SPI slave timing values
Symbol
Parameter
Value(1)
Min
Max
Unit
tc(SPC)
SPI clock cycle
100
ns
fc(SPC)
SPI clock frequency
10
MHz
tsu(CS)
CS setup time
5
th(CS)
CS hold time
8
tsu(SI)
SDI input setup time
5
th(SI)
SDI input hold time
15
ns
tv(SO)
SDO valid output time
50
th(SO)
SDO output hold time
6
tdis(SO)
SDO output disable time
50
1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not
tested in production
Figure 3. SPI slave timing diagram (2)
CS (3)
SPC (3)
tsu(CS)
SDI (3)
SDO (3)
tc(SPC)
tsu(SI)
th(SI)
MSB IN
tv(SO)
MSB OUT
th(SO)
(3)
th(CS)
(3)
LSB IN
(3)
tdis(SO)
LSB OUT
(3)
2. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both Input and Output port
3. When no communication is on-going, data on CS, SPC, SDI and SDO are driven by internal pull-up resistors
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