LD39080(2017) 데이터 시트보기 (PDF) - STMicroelectronics

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LD39080
(Rev.:2017)

Ultra low drop BiCMOS voltage regulator

STMicroelectronics 

Pin configuration

2

Pin configuration

Figure 2. Pin connections (top view)

LD39080

PPAK

Table 2. Pin description

Pin

Symbol

Note

5

ADJ

Error amplifier input pin for VO from 1.22 to 5.0 V

2

VI

LDO input voltage: VI from 2.5 V to 6 V, CI=1 µF not farther than 1 cm from

input pin

4

VO

LDO output voltage pins, with minimum CO = 2.2 µF needed for stability

(refer to CO vs ESR stability chart)

1

VINH

Inhibit input voltage: on mode when VINH  2 V, off mode when

VINH  0.3 V (do not leave it floating, not internally pulled down/up)

3

GND

Common ground

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DocID13158 Rev 3

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