LAN91C95 데이터 시트보기 (PDF) - SMSC -> Microchip
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LAN91C95 Datasheet PDF : 144 Pages
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BUFFER MEMORY
The logical addresses for RAM access are divided
into TX area and RX area. Each one of the areas
is 1.536 kbytes long and accommodates one
maximum size Ethernet packet.
The TX area is seen by the CPU as a window
through which packets can be loaded into memory
before queuing them in the TX FIFO of packets.
The TX area can also be used to examine the
transmit completion status after packet
transmission.
The RX area is associated to the output of the RX
FIFO of packets, and is used to access receive
packet data and status information.
The logical address is specified by loading the
address pointer register. The pointer can
automatically increment on accesses.
All accesses to the RAM are done via I/O space. A
bit in the address pointer also specifies if the
address refers to the TX or RX area.
In the TX area, the host CPU has access to the
next transmit packet being prepared for
transmission. In the RX area, it has access to the
first receive packet not processed by the CPU yet.
The FIFO of packets, existing beneath the TX and
RX areas, is managed by the MMU. The MMU
dynamically allocates and releases memory to be
used by the transmit and receive functions.
The MMU related parameters for the LAN91C95
are:
RAM size
Max. number of packets
Max. pages per packet
Max. number of pages
Page size
6 kbytes (internal)
24
6
24
256 bytes
24
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