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L74VHC1GT08 데이터 시트보기 (PDF) - Leshan Radio Company,Ltd

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L74VHC1GT08
LRC
Leshan Radio Company,Ltd LRC
L74VHC1GT08 Datasheet PDF : 6 Pages
1 2 3 4 5 6
LESHAN RADIO COMPANY, LTD.
2-Input AND Gate
with LSTTL–Compatible Inputs
L74VHC1GT08
The L74VHC1G08 is an advanced high speed CMOS 2–input AND gate fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power issipation.
The internal circuit is composed of three stages, including an open drain output which provides the ability to set output switching level.
This allows the L74VHC1GT08 to be used to interface 5 V circuits to circuits of any voltage between V CC and 7 V using an external
resistor and power supply.
The device input is compatible with TTL–type input thresholds and the output has a full 5.0 V CMOS level output swing. The input
protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic–level translator from
3.0 V CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while operating at the high–voltage power
supply.
The L74VHC1GT08 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This
allows the L74VHC1GT08 to be used to interface 5 V circuits to 3 V circuits. The output structures also provide protection when
V CC = 0 V. These input and output structures help prevent device destruction caused by supply voltage – input/output voltage mismatch,
battery backup, hot insertion, etc.
• High Speed: t PD = 3.5 ns (Typ) at V CC = 5 V
• Low Power Dissipation: I CC = 2 mA (Max) at T A = 25°C
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Pin and Function Compatible with Other Standard Logic Families
• Chip Complexity: FETs = 62; Equivalent Gates = 15
MARKING DIAGRAMS
5
4
1
2
3
SC–88A / SOT–353/SC–70
DF SUFFIX
V2d
5
4
1
2
3
TSOP–5/SOT–23/SC–59
DT SUFFIX
PIN ASSIGNMENT
1
IN B
2
IN A
3
GND
4
OUT Y
5
V CC
Pin 1
d = Date Code
Figure 1. Pinout (Top View)
V2d
Figure 2. Logic Symbol
Pin 1
d = Date Code
FUNCTION TABLE
Inputs
A
B
L
L
L
H
H
L
H
H
Output
Y
L
L
L
H
ORDERING INFORMATION
See detailed ordering and shipping information in the
package dimensions section on page 5of this data sheet.
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