L6712ADTR(2004) 데이터 시트보기 (PDF) - STMicroelectronics
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L6712ADTR Datasheet PDF : 27 Pages
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L6712A L6712
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
VCC, VCCDR To PGND
VBOOT-VPHASE Boot Voltage
VUGATE1-VPHASE1
VUGATE2-VPHASE2
LGATE1, PHASE1, LGATE2, PHASE2 to PGND
VID0 to VID2
All other pins to PGND
VPHASEx
Sustainable Peak Voltage. T<20ns @ 600kHz
UGATEX Pins
OTHER PINS
Maximum Withstanding Voltage Range
Test Condition: CDF-AEC-Q100-002”Human Body Model”
Acceptance Criteria: “Normal Performance”
Value
15
15
15
-0.3 to Vcc+0.3
-0.3 to 5
-0.3 to 7
26
±1500
±2000
Unit
V
V
V
V
V
V
V
V
V
THERMAL DATA
Symbol
Rthj-amb
Tmax
Tstg
Tj
PMAX
Parameter
Thermal Resistance Junction to Ambient
4 layer PCB (2s2p)
Maximum junction temperature
Storage temperature range
Junction Temperature Range
Max power dissipation at Tamb = 25°C
PIN CONNECTION (Top view)
SO28
60
VFQFPN36 Unit
30
°C/W
150
150
°C
-40 to 150 -40 to 150
°C
-40 to 125 -40 to 125
°C
2
3.5
W
LGATE1
VCCDR
PHASE1
UGATE1
BOOT1
VCC
SGND
COMP
FB
DROOP
REF_IN/OUT
VSEN
ISEN1
PGNDS1
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
SO28
PGND
LGATE2
PHASE2
UGATE2
BOOT2
PGOOD
VID2
VID1
VID0
FBR
FBG
OSC/INH/FAULT
ISEN2
PGNDS2
UGATE2
PHASE2
LGATE2
PGND
PGND
LGATE1
VCCDR
PHASE1
UGATE1
27 26 25 24 23 22 21 20 19
28
18
29
17
30
16
31
15
32
14
33
13
34
12
35
11
36
10
123456789
OSC
N.C.
ISEN2
PGNDS2
PGNDS1
ISEN1
VSEN
REF_IN/OUT
N.C.
VFQFPN-36
Corner Pin internally connected to the Exposed Pad.
2/27
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