KM681000EL 데이터 시트보기 (PDF) - Samsung
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KM681000EL Datasheet PDF : 10 Pages
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KM681000E Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS( Test Load and Input/Output Reference)
Input pulse level : 0.8 to 2.4V
Input rising and falling time : 5ns
Input and output reference voltage :1.5V
Output load(see right) : CL=100pF+1TTL
CL=50pF+1TTL
CL1)
1. Including scope and jig capacitance
AC CHARACTERISTICS (VCC=4.5~5.5V, Commercial Product : TA=0 to 70°C, Industrial Product : TA=-40 to 85°C)
Parameter List
Read
Write
Read cycle time
Address access time
Chip select to output
Output enable to valid output
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
Chip select to end of write
Address set-up time
Address valid to end of write
Write pulse width
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
Symbol
tRC
tAA
tCO1, tCO2
tOE
tLZ
tOLZ
tHZ
tOHZ
tOH
tWC
tCW
tAS
tAW
tWP
tWR
tWHZ
tDW
tDH
tOW
Speed Bins
55ns
70ns
Min
Max
Min
Max
55
-
70
-
-
55
-
70
-
55
-
70
-
25
-
35
10
-
10
-
5
-
5
-
0
20
0
25
0
20
0
25
10
-
10
-
55
-
70
-
45
-
60
-
0
-
0
-
45
-
60
-
40
-
50
-
0
-
0
-
0
20
0
25
20
-
25
-
0
-
0
-
5
-
5
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DATA RETENTION CHARACTERISTICS
Item
Symbol
Test Condition
Min Typ Max Unit
Vcc for data retention
VDR
CS1≥Vcc-0.2V1)
2.0
-
5.5 V
KM681000EL
-
-
20
Data retention current
IDR
Vcc=3.0V, CS1≥Vcc-0.2V1)
KM681000EL-L -
KM681000ELI
-
-
10
µA
-
25
KM681000ELI-L -
-
10
Data retention set-up time
Recovery time
tSDR
tRDR
See data retention waveform
0
-
-
ms
5
-
-
1. CS1≥Vcc-0.2V, CS2≥Vcc-0.2V(CS1 controlled) or CS2≤0.2V(CS2 controlled)
5
Revision 1.01
December 1999
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