KA7500CDTF 데이터 시트보기 (PDF) - Fairchild Semiconductor

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KA7500CDTF

SMPS Controller

Fairchild Semiconductor 

Physical Dimensions

A

19.68

18.66

16

9

6.60

6.09

1

8

(0.40)

TOP VIEW

0.38 MIN

5.33 MAX

3.42

3.17

3.81

2.92

2.54

0.58 A

0.35

1.78

1.14

17.78

SIDE VIEW

NOTES: UNLESS OTHERWISE SPECIFIED

A THIS PACKAGE CONFORMS TO

JEDEC MS-001 VARIATION BB

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS ARE EXCLUSIVE OF BURRS,

MOLD FLASH, AND TIE BAR PROTRUSIONS

D) CONFORMS TO ASME Y14.5M-1994

E) DRAWING FILE NAME: N16EREV1

8.13

7.62

15

0.35

0

0.20

8.69

Figure 4. 16-Lead Dual Inline Package (DIP

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify

or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically

the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

© 2003 Fairchild Semiconductor Corporation

KA7500C • Rev. 1.0.2

7

www.fairchildsemi.com

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