K4E641612C-L 데이터 시트보기 (PDF) - Samsung
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K4E641612C-L Datasheet PDF : 36 Pages
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K4E661612C,K4E641612C
CMOS DRAM
NOTES
1. An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
2. Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition
times are measured between VIH(min) and VIL(max) and are assumed to be 2ns for all inputs.
3. Measured with a load equivalent to 1 TTL load and 100pF.
4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.
5. Assumes that tRCD≥tRCD(max).
6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol.
7. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electric charac-
teristics only. If tWCS≥tWCS(min), the cycles is an early write cycle and the data output will remain high impedance for the
duration of the cycle. If tCWD≥tCWD(min), tRWD≥tRWD(min) and tAWD≥tAWD(min), then the cycle is a read-modify-write cycle
and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the
condition of the data out is indeterminate.
8. Either tRCH or tRRH must be satisfied for a read cycle.
9. This parameters are referenced to the CAS leading edge in early write cycles and to the W falling edge in OE controlled write
cycle and read-modify-write cycles.
10. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If
tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.
11. These specifiecations are applied in the test mode.
12. In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters
should be specified in test mode cycles by adding the above value to the specified value in this data sheet.
13. tASC, tCAH are referenced to the earlier CAS falling edge.
14. tCP is specified from the last CAS rising edge in the previous cycle to the first CAS falling edge in the next cycle.
15. tCWD is referenced to the later CAS falling edge at word read-modify-write cycle.
K4E64(6)1612C Truth Table
RAS
LCAS
UCAS
W
H
X
X
X
L
H
H
X
L
L
H
H
L
H
L
H
L
L
L
H
L
L
H
L
L
H
L
L
L
L
L
L
L
L
L
H
OE
DQ0 - DQ7
DQ8-DQ15
X
Hi-Z
Hi-Z
X
Hi-Z
Hi-Z
L
DQ-OUT
Hi-Z
L
Hi-Z
DQ-OUT
L
DQ-OUT
DQ-OUT
H
DQ-IN
-
H
-
DQ-IN
H
DQ-IN
DQ-IN
H
Hi-Z
Hi-Z
STATE
Standby
Refresh
Byte Read
Byte Read
Word Read
Byte Write
Byte Write
Word Write
-
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