IW4019B 데이터 시트보기 (PDF) - Unspecified
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IW4019B Datasheet PDF : 5 Pages
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TECHNICAL DATA
Quad AND/OR Select Gate
High-Voltage Silicon-Gate CMOS
IW4019B
The IW4019B types consist of four AND/OR select gate
configurations, each consisting of two 2-input AND gates driving a single
2-input gate. Selection is accomplished by control bits Sa and Sb .In
addition to selection of either channel A or channel B information, the
control bits can be applied simultaneously to accomplish the logical A + B
function
• Operating Voltage Range: 3.0 to 18 V
• Maximum input current of 1 µA at 18 V over full package-temperature
range; 100 nA at 18 V and 25°C
• Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
ORDERING INFORMATION
IW4019BN Plastic
IW4019BDW SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
PIN 16 =VCC
PIN 8 = GND
FUNCTION TABLE
Inputs
Outputs
Sa
Sb
AB
Y
H
L
HX
H
H
L
LX
L
L
H
XH
H
L
H
XL
L
L
L
XX
L
H
H
LL
L
H
H
LH
H
H
H
HL
H
H
H
HH
H
1
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