ISPLSI2032A-80LJ44 데이터 시트보기 (PDF) - Lattice Semiconductor
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ISPLSI2032A-80LJ44 Datasheet PDF : 15 Pages
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Specifications ispLSI 2032/A
Pin Description
NAME
44-PIN PLCC 44-PIN TQFP 48-PIN TQFP
PIN NUMBERS PIN NUMBERS PIN NUMBERS
DESCRIPTION
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
GOE 0
Y0
RESET/Y1
15, 16, 17, 18,
19, 20, 21, 22,
25, 26, 27, 28,
29, 30, 31, 32,
37, 38, 39, 40,
41, 42, 43, 44,
3, 4, 5, 6,
7, 8, 9, 10
2
11
35
9, 10, 11, 12,
13, 14, 15, 16,
19, 20, 21, 22,
23, 24, 25, 26,
31 32, 33, 34,
35, 36, 37, 38,
41, 42, 43, 44,
1, 2, 3, 4
40
5
29
9, 10, 11, 13,
14, 15, 16, 17,
20, 21, 22, 23,
25, 26, 27, 28,
33, 34, 35, 37,
38, 39, 40, 41,
44, 45, 46, 47,
1, 2, 3, 4
43
5
31
Input/Output Pins — These are the general purpose
I/O pins used by the logic array.
NS Global Output Enable input pin.
IG Dedicated Clock input. This clock input is connected to
one of the clock inputs of all the GLBs on the device.
S This pin performs two functions:
E - Dedicated clock input. This clock input is brought
into the Clock Distribution Network, and can optionally
D be routed to any GLB and/or I/O cell on the device.
ispEN
13
7
7
- Active Low (0) Reset pin which resets all of the GLB
and I/O registers in the device.
W Input — Dedicated in-system programming enable
input pin. This pin is brought low to enable the
E programming mode. The MODE, SDI, SDO and SCLK
Ncontrols become active.
SDI/IN 02
MODE
SDO/IN 12
SCLK/Y22
GND
VCC
NC1
14
FOR 36
E 24
032 33
LSI 2 1, 23
isp 12, 34
8
30
18
27
17, 39
6, 28
8
32
19
29
18, 42
6, 30
12, 24, 36, 48
Input — This pin performs two functions. When ispEN
is logic low, it functions as an input pin to load
programming data into the device. SDI/IN0 also is used
as one of the two control pins for the isp state machine.
When ispEN is high, it functions as a dedicated input
pin.
Input — When in ISP Mode, controls operation of ISP
state machine.
Output/Input — This pin performs two functions. When
ispEN is logic low, it functions as an output pin to read
serial shift register data. When ispEN is high, it
functions as a dedicated input pin.
Input — This pin performs two functions. When
ispEN is logic low, it functions as a clock pin for the
Serial Shift Register. When ispEN is high, it
functions as a dedicated clock input. This clock input
is brought into the Clock Distribution Network and
can be routed to any GLB and/or I/O cell on the
device.
Ground (GND)
VCC
No Connect.
1. NC pins are not to be connected to any active signals, VCC or GND.
USE 2. Pins have dual function capability.
Table 2-0002A-08isp/2032
11
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