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ISL97651

4-Channel Integrated LCD Supply

Intersil 

ISL97651

After CDLY reaches the 4th peak, the internal N-FET is

turned-on and produces an initial current output of

IDELB_ON1 (~50µA). This current allows the user to control

the turn-on inrush current into the AVDD_delay supply

capacitors by a suitable choice of C4. This capacitor can

provide extra delay and also filter out any noise coupled into

the gate of M0, avoiding spurious turn-on, however, C4 must

not be so large that it prevents DELB reaching 0.6V by the

end of the start-up sequence on CDLY, else a fault time-out

ramp on CDLY will start. A value of 22nF is typically required

for C4. The 0.6V threshold is used by the chip's fault

detection system and if V(DELB) is still above 0.6V at the

end of the power sequencing then a fault time-out ramp will

be initiated on CDLY.

When the voltage at DELB falls below ~0.6V it's current is

increased to IDELB_ON2 (~1.4mA) to firmly pull the DELB

voltage to ground.

If the maximum VGS voltage of M0 is less than the AVDD

voltage being used, then a resistor may be inserted between

the DELB pin and the gate of M0 such that it's potential

divider action with R4 ensures the gate/source stays below

VGS(M0)max. This additional resistor allows much larger

values of C4 to be used, and hence longer AVDD delay,

without affecting the fault protection on DELB.

Component Selection for Start-up Sequencing and

Fault Protection

The CREF capacitor is typically set at 220nF and is required

to stabilize the VREF output. The range of CREF is from

22nF to 1µF and should not be more than five times the

capacitor on CDEL to ensure correct start-up operation.

The CDEL capacitor is typically 220nF and has a usable

range from 47nF minimum to several microfarads – only

limited by the leakage in the capacitor reaching µA levels.

CDEL should be at least 1/5 of the value of CREF (see

above). Note with 220nF on CDEL the fault time-out will be

typically 50ms and the use of a larger/smaller value will vary

this time proportionally (e.g., 1µF will give a fault time-out

period of typically 230ms).

Over-Temperature Protection

An internal temperature sensor continuously monitors the

die temperature. In the event that the die temperature

exceeds the thermal trip point of +150°C, the device will shut

down. Operation with die temperatures between +125°C and

+150°C can be tolerated for short periods of time, however,

in order to maximize the operating life of the IC, it is

recommended that the effective continuous operating

junction temperature of the die should not exceed +125°C.

Layout Recommendation

The device’s performance including efficiency, output noise,

transient response and control loop stability is dramatically

affected by the PCB layout. PCB layout is critical, especially

at high switching frequency.

There are some general guidelines for layout:

1. Place the external power components (the input

capacitors, output capacitors, boost inductor and output

diodes, etc.) in close proximity to the device. Traces to

these components should be kept as short and wide as

possible to minimize parasitic inductance and resistance.

2. Place VREF and VDC bypass capacitors close to the pins.

3. Reduce the loop with large AC amplitudes and fast slew

rate.

4. The feedback network should sense the output voltage

directly from the point of load, and be as far away from LX

node as possible.

5. The power ground (PGND) and signal ground (SGND)

pins should be connected at only one point.

6. The exposed die plate, on the underneath of the

package, should be soldered to an equivalent area of

metal on the PCB. This contact area should have multiple

via connections to the back of the PCB as well as

connections to intermediate PCB layers, if available, to

maximize thermal dissipation away from the IC.”

7. To minimize the thermal resistance of the package when

soldered to a multi-layer PCB, the amount of copper track

and ground plane area connected to the exposed die

plate should be maximized and spread out as far as

possible from the IC. The bottom and top PCB areas

especially should be maximized to allow thermal

dissipation to the surrounding air.

8. Minimize feedback input track lengths to avoid switching

noise pick-up.

A demo board is available to illustrate the proper layout

implementation.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

18

FN7493.3

April 24, 2009

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