ISL97645A(2010) 데이터 시트보기 (PDF) - Intersil

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ISL97645A
(Rev.:2010)

Boost + VON Slice + VCOM + Reset

Intersil 

ISL97645A

.

VGH

VVGGHH_M_M

VDD1

RE

CE

x240

200µA

EnGPM1

VREF

VFLK

CONTROL

AND

TIMING

FIGURE 16. GATE PULSE MODULATOR CIRCUIT BLOCK DIAGRAM

Vin

UVLO

Threshold

0

VGH

RESET

VDPM

1.215V

VFLK

VGH_M

VGH

VGL

Power on delay time is

controlled by CDPM

Slope is controlled

by RE

Delay tim e is

controlled by CE

VGH_M is forced to

VGH when RESET

goes to low AND

V G H > 2 .5 V

FIGURE 17. GATE PULSE MODULATOR TIMING DIAGRAM

13

FN6353.1

October 21, 2010

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